Datasheet > QL4090-4PB456C

QL4090-4PB456C

更新时间： 2024-11-11 23:30:39

品牌	Logo	应用领域
其他 - ETC		现场可编程门阵列可编程逻辑栅时钟
页数	文件大小	规格书
12页	282K
描述
Field Programmable Gate Array (FPGA)

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QL4090-4PB456C 数据手册

QL4090 - QuickRAM^TM

90,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density, and Embedded RAM

QL4090 - QuickRAM

EVICE

HIGHLIGHTS

Device Highlights

High Performance & High Density

■ 90,000 Usable PLD Gates with 316 I/Os

1,584

High Speed

Logic Cells

RAM

Blocks

■ 300 MHz 16-bit Counters, 400 MHz Datapaths,

}

160+ MHz FIFOs

■ 0.35µm four-layer metal non-volatile CMOS process for

smallest die sizes

Interface

High Speed Embedded SRAM

■ 22 dual-port RAM modules, organized in user-config-

FIGURE 1. QuickRAM Block Diagram

urable 1,152 bit blocks

■ 5ns access times, each port independently accessible

■ Fast and effecient for FIFO, RAM, and ROM functions

RCHITECTURE

VERVIEW

Architecture Overview

The QuickRAM family of ESPs (Embedded Standard

Products) offers FPGA logic in combination with Dual-

Port SRAM modules. The QL4090 is a 90,000

usable PLD gate member of the QuickRAM family of

ESPs. QuickRAM ESPs are fabricated on a 0.35mm

four-layer metal process using QuickLogic’s patented

ViaLink^TMtechnology to provide a unique combina-

tion of high performance, high density, low cost, and

extreme ease-of-use.

Easy to Use / Fast Development Cycles

■ 100% routable with 100% utilization and complete

pin-out stability

■ Variable-grain logic cells provide high performance and

100% utilization

■ Comprehensive design tools include high quality

Verilog/VHDL synthesis

Advanced I/O Capabilities

■ Interfaces with both 3.3 volt and 5.0 bolt devices

The QL4090 contains 1,584 logic cells and 22 dual

port RAM modules (see Figure 1). Each RAM module

has 1,152 RAM bits, for a total of 25,344 bits. RAM

Modules are Dual Port (one read port, one write port)

and can be configured into one of four modes: 64

(deep) x18 (wide), 128x9, 256x4, or 512x2 (see Fig-

ure 2). With a maximum of 204 I/Os, the QL4090 is

available in 208-PQFP, 240-pin PQFP and 456-pin

PBGA packages.

■ PCI compliant with 3.3V and 5.0V busses for -1/-2/-3/-4

speed grades

■ Full JTAG boundary scan

■ Registered I/O cells with individually controlled clocks and

output enables

Designers can cascade multiple RAM modules to

increase the depth or width allowed in single modules

by connecting corresponding address lines together

and dividing the words between modules (see Figure

3). This approach allows up to 512-deep configura-

tions as large as 16 bits wide in the smallest Quick-

RAM device and 44 bits wide in the largest device.

6-55

QL4090 Rev G

12 3 4 5 6 7...12

中文翻译

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与QL4090-4PB456C相关器件

型号	品牌	获取价格	描述	数据表
QL4090-4PB456I	ETC	获取价格	FPGA\|1584-CELL\|CMOS\|BGA\|456PIN\|PLASTIC
QL4090-4PQ208C	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL4090-4PQ208I	ETC	获取价格	FPGA\|1584-CELL\|CMOS\|QFP\|208PIN\|PLASTIC
QL4090-4PQ240C	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL4090-4PQ240I	ETC	获取价格	Field Programmable Gate Array (FPGA)
QL4150PB456	ETC	获取价格	ASIC
QL4150PQ208	ETC	获取价格	ASIC
QL4150PQ240	ETC	获取价格	ASIC
QL422YW048V	CDE	获取价格	QL422YW048V
QL4420LEV-1500.0M	PLETRONICS	获取价格	XO, Clock,

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