Datasheet > QL4090-1PB456I

QL4090-1PB456I

更新时间： 2024-11-11 23:30:39

品牌	Logo	应用领域
其他 - ETC		可编程逻辑栅时钟
页数	文件大小	规格书
22页	539K
描述
FPGA\|1584-CELL\|CMOS\|BGA\|456PIN\|PLASTIC

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QL4090-1PB456I 数据手册

QL4090 QuickRAM Data Sheet

90,000 Usable PLD Gate QuickRAM ESP Combining Performance,

Density and Embedded RAM

• • • • • •

Advanced I/O Capabilities

Device Highlights

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V busses

High Performance & High Density

for -1/-2/-3/-4 speed grades

• 90,000 Usable PLD Gates with 316 I/Os

• Full JTAG boundary scan

• 300 MHz 16-bit Counters, 400 MHz

• I/O Cells with individually controlled

Datapaths, 160+ MHz FIFOs

Registered Input Path and Output Enables

• 0.35µm four-layer metal non-volatile CMOS

process for smallest die sizes

High Speed Embedded SRAM

• 22 dual-port RAM modules, organized in

user-configurable 1,152 bit blocks

• 5 ns access times, each port independently

RAM

Blocks

1,584

High Speed

Logic Cells

accessible

• Fast and efficient for FIFO, RAM, and ROM

functions

Easy to Use / Fast Development

Cycles

Interface

• 100% routable with 100% utilization and

Figure 1: QuickRAM Block Diagram

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high

quality Verilog/VHDL synthesis

•

www.quicklogic.com

12 3 4 5 6 7...22

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