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QL4058 PDF预览

QL4058

更新时间: 2024-11-11 06:06:15
品牌 Logo 应用领域
其他 - ETC
页数 文件大小 规格书
23页 539K
描述
58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM

QL4058 数据手册

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QL4058 QuickRAM Data Sheet  
58,000 Usable PLD Gate QuickRAM ESP Combining Performance,  
Density and Embedded RAM  
• • • • • •  
Advanced I/O Capabilities  
Device Highlights  
Interfaces with both 3.3 V and 5.0 V devices  
PCI compliant with 3.3 V and 5.0 V busses  
High Performance & High Density  
for -1/-2/-3/-4 speed grades  
58,000 Usable PLD Gates with 252 I/Os  
Full JTAG boundary scan  
300 MHz 16-bit Counters, 400 MHz  
I/O Cells with individually controlled  
Datapaths, 160+ MHz FIFOs  
Registered Input Path and Output Enables  
0.35 µm four-layer metal non-volatile  
CMOS process for smallest die sizes  
High Speed Embedded SRAM  
18 dual-port RAM modules, organized in  
user-configurable 1,152 bit blocks  
5 ns access times, each port independently  
18  
RAM  
Blocks  
1,008  
High Speed  
Logic Cells  
accessible  
Fast and efficient for FIFO, RAM, and ROM  
functions  
Easy to Use / Fast Development  
Cycles  
Interface  
100% routable with 100% utilization and  
Figure 1: QuickRAM Block Diagram  
complete pin-out stability  
Variable-grain logic cells provide high  
performance and 100% utilization  
Comprehensive design tools include high  
quality Verilog/VHDL synthesis  
© 2002 QuickLogic Corporation  
www.quicklogic.com  
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