Datasheet > Q67100-Q519

Q67100-Q519

更新时间： 2024-01-18 23:14:21

品牌	Logo	应用领域
英飞凌 - INFINEON		存储
页数	文件大小	规格书
22页	194K
描述
1 M x 1-Bit Dynamic RAM Low Power 1 M ⅴ 1-Bit Dynamic RAM

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中文翻译

获取价格

数据手册

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Q67100-Q519 数据手册

1 M × 1-Bit Dynamic RAM

Low Power 1 M × 1-Bit Dynamic RAM

HYB 511000BJ-50/-60/-70

HYB 511000BJL-50/-60/-70

Advanced Information

• 1 048 576 words by 1-bit organization

• Fast access and cycle time

50 ns access time

• Single + 5 V (± 10 %) supply with a built-in

V_BBgenerator

• Output unlatched at cycle end allows two-

95 ns cycle time (-50 version)

60 ns access time

130 ns cycle time (-60 version)

70 ns access time

dimensional chip selection

• Common I/O capability using “early write”

operation

• Read-modify-write, CAS-before-RAS

refresh, RAS-only refresh, hidden-refresh,

fast page mode capability and test mode

capability

130 ns cycle time (-70 version)

• Fast page mode cycle time

35 ns (-50 version)

40 ns (-60 version)

45 ns (-70 version)

• All inputs, outputs and clocks

TTL-compatible

• Low power dissipation

max. 495 mW active (-50 version)

max. 440 mW active (-60 version)

max. 385 mW active (-70 version)

max. 5.5 mW standby

• 512 refresh cycles/8 ms

512 refresh cycles/64 ms

for L-version only

• Plastic Packages:

P-SOJ-26/20-1

max. 1.1 mW standby for L-version

Ordering Information

Type

Ordering Code

Q67100-Q1056

Q67100-Q518

Q67100-Q519

on request

Package

Description

HYB 511000BJ-50

HYB 511000BJ-60

HYB 511000BJ-70

HYB 511000BJL-50

HYB 511000BJL-60

HYB 511000BJL-70

P-SOJ-26/20-1

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

DRAM (access time 50 ns)

DRAM (access time 60 ns)

DRAM (access time 70 ns)

Q67100-Q526

Q67100-Q527

Semiconductor Group

01.95

12 3 4 5 6 7...22

中文翻译

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