PT4850 Series
25-A Triple Output Isolated DC/DC
Converter For Logic Applications
SLTS166C - FEBRUARY 2002 - REVISED MARCH 2003
Features
• Triple Logic Voltage Outputs
• Dual Logic On/Off Control
• Fixed Frequency Operation
• Solderable Space Saving Package:
1.97 sq. in. PCB Area (suffix N)
(Independently Regulated !)
• Input Voltage Range:
36V to 75V
• 1500VDC Isolation
• IPC Lead Free 2
• Safety Approvals Pending:
UL60950
• Over-Current Protection
• Over-Voltage Protection
• Over-Temperature Shutdown
• Under-Voltage Lockout
• Independently Adjustable Outputs
CSA 22.2 950
VDE EN60950
Description
Ordering Information
PT4851o = +3.3/+2.5/+1.5V
PT4852o = +3.3/+1.8/+1.5V
PT4853o = +3.3/+2.5/+1.2V
PT4854o = +3.3/+1.8/+1.2V
PT4855o = +3.3/+1.5/+1.2V
PT4856o = +5.0/+3.3/+1.5V
The PT4850 Excalibur™ power
modules are a series of isolated triple-
output DC/DC converters that
operate from a standard (–48V)
central office supply. These modules
are rated for a combined output of
up to 25A, and were designed for
powering mixed logic applications.
The triple-output voltage provides
a compact multiple-output power
supply in a single DC/DC module.
Output voltage options include
a low-voltage output for a DSP or
ASIC core, and two additional supply
voltages for the I/O, and other func-
tions.
The PT4850 series incorporates
many features to simplify system
integration. These include a flexible
On/Off enable control, input under-
voltage lockout and over-temperature
protection. All outputs are current
limited and short-circuit protected,
and are internally sequenced to meet
the power-up and power-down re-
quirements of popular DSP ICs.
The PT4850 series is housed in
a space-saving solderable case. The
module requires no external heat
sink. Both vertical and horizontal
pin configurations are available, in-
cluding surface mount.
PT Series Suffix
(PT1234x)
Case/Pin
Order
Package
Code
Configuration
Suffix
Vertical
Horizontal
SMD
N
A
C
(EKD)
(EKA)
(EKC)
(Reference the applicable package code drawing for
the dimensions and PC layout)
Standard Application
PT4850
I/O
9,10,11
8
+Vo1
V1 Adj
COM
+VIN
1
+
+VIN
Co1
12,13,14
25
V2Sense
+Vo2
Logic
Core
15,16
17
+
DSL, DSP,
or ASIC
Chipset
CIN
4
V2 Adj
EN 2
+
Co2
Q1
3
EN 1
24
V3Sense
+Vo3
22,23
21
–VIN
2
–VIN
V3 Adj
+
Co3
1 =Inhibit
COM
18,19,20
Cin =Optional
Co1, Co2, Co3 =Optional. See specifications
EN1 & EN2 operation: See application notes
For technical support and more information, see inside back cover or visit www.ti.com