Datasheet > PSD854220MT

PSD854220MT

更新时间： 2024-11-05 22:36:39

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
110页	1732K
描述
Flash In-System Programmable ISP Peripherals For 8-bit MCUs

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PSD854220MT 数据手册

PSD813F2, PSD833F2

PSD834F2, PSD853F2, PSD854F2

Flash In-System Programmable (ISP)

Peripherals for 8-bit MCUs, 5V

PRELIMINARY DATA

FEATURES SUMMARY

■

FLASH IN-SYSTEM PROGRAMMABLE (ISP)

Figure 1. Packages

PERIPHERAL FOR 8-BIT MCUS

■

DUAL BANK FLASH MEMORIES

–

UP TO 2 Mbit OF PRIMARY FLASH

MEMORY (8 Uniform Sectors, 32K x8)

UP TO 256 Kbit SECONDARY FLASH

MEMORY (4 Uniform Sectors)

Concurrent operation: READ from one

memory while erasing and writing the

other

PQFP52 (M)

■

UP TO 256 Kbit BATTERY-BACKED SRAM

27 RECONFIGURABLE I/O PORTS

ENHANCED JTAG SERIAL PORT

PLD WITH MACROCELLS

–

Over 3000 Gates of PLD: CPLD and

DPLD

CPLD with 16 Output Macrocells (OMCs)

and 24 Input Macrocells (IMCs)

DPLD - user defined internal chip select

decoding

PLCC52 (J)

■

27 INDIVIDUALLY CONFIGURABLE I/O

PORT PINS

The can be used for the following functions:

–

MCU I/Os

PLD I/Os

Latched MCU address output

Special function I/Os.

16 of the I/O ports may be configured as

open-drain outputs.

TQFP64 (U)

■

IN-SYSTEM PROGRAMMING (ISP) WITH

JTAG

–

Built-in JTAG compliant serial port allows

full-chip In-System Programmability

Efficient manufacturing allow easy

product testing and programming

■

HIGH ENDURANCE:

–

100,000 Erase/WRITE Cycles of Flash

Memory

Use low cost FlashLINK cable with PC

■

PAGE REGISTER

–

1,000 Erase/WRITE Cycles of PLD

15 Year Data Retention

Internal page register that can be used to

expand the microcontroller address space

by a factor of 256

■

5V±10% SINGLE SUPPLY VOLTAGE

STANDBY CURRENT AS LOW AS 50µA

PROGRAMMABLE POWER MANAGEMENT

June 2004

1/110

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

12 3 4 5 6 7...110

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