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PSD833F2VA-20U PDF预览

PSD833F2VA-20U

更新时间: 2024-11-06 20:00:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 外围集成电路
页数 文件大小 规格书
110页 837K
描述
128KX8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64, PLASTIC, TQFP-64

PSD833F2VA-20U 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:PLASTIC, TQFP-64
针数:64Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.83最长访问时间:2e-7 ns
JESD-30 代码:S-PQFP-G64长度:14 mm
I/O 线路数量:27端口数量:4
端子数量:64最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.63SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
电源:3.3 V认证状态:Not Qualified
ROM大小(位):1310720 Bits座面最大高度:1.54 mm
最大待机电流:0.0001 A子类别:Other Microprocessor ICs
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD紫外线可擦:N
宽度:14 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

PSD833F2VA-20U 数据手册

 浏览型号PSD833F2VA-20U的Datasheet PDF文件第2页浏览型号PSD833F2VA-20U的Datasheet PDF文件第3页浏览型号PSD833F2VA-20U的Datasheet PDF文件第4页浏览型号PSD833F2VA-20U的Datasheet PDF文件第5页浏览型号PSD833F2VA-20U的Datasheet PDF文件第6页浏览型号PSD833F2VA-20U的Datasheet PDF文件第7页 
PSD813F2, PSD833F2  
PSD834F2, PSD853F2, PSD854F2  
Flash In-System Programmable (ISP)  
Peripherals for 8-bit MCUs, 5V  
FEATURES SUMMARY  
FLASH IN-SYSTEM PROGRAMMABLE (ISP)  
Figure 1. Packages  
PERIPHERAL FOR 8-BIT MCUS  
DUAL BANK FLASH MEMORIES  
UP TO 2 Mbit OF PRIMARY FLASH  
MEMORY (8 Uniform Sectors, 32K x8)  
UP TO 256 Kbit SECONDARY FLASH  
MEMORY (4 Uniform Sectors)  
Concurrent operation: READ from one  
memory while erasing and writing the  
other  
PQFP52 (M)  
UP TO 256 Kbit BATTERY-BACKED SRAM  
27 RECONFIGURABLE I/O PORTS  
ENHANCED JTAG SERIAL PORT  
PLD WITH MACROCELLS  
Over 3000 Gates of PLD: CPLD and  
DPLD  
CPLD with 16 Output Macrocells (OMCs)  
and 24 Input Macrocells (IMCs)  
DPLD - user defined internal chip select  
decoding  
PLCC52 (J)  
27 INDIVIDUALLY CONFIGURABLE I/O  
PORT PINS  
The can be used for the following functions:  
MCU I/Os  
PLD I/Os  
Latched MCU address output  
Special function I/Os.  
16 of the I/O ports may be configured as  
open-drain outputs.  
TQFP64 (U)  
IN-SYSTEM PROGRAMMING (ISP) WITH  
JTAG  
Built-in JTAG compliant serial port allows  
full-chip In-System Programmability  
Efficient manufacturing allow easy  
product testing and programming  
HIGH ENDURANCE:  
100,000 Erase/WRITE Cycles of Flash  
Memory  
Use low cost FlashLINK cable with PC  
PAGE REGISTER  
1,000 Erase/WRITE Cycles of PLD  
15 Year Data Retention  
Internal page register that can be used to  
expand the microcontroller address space  
by a factor of 256  
5V 10ꢀ SINGLE SUPPLY VOLTAGE  
STANDBY CURRENT AS LOW AS 50µA  
PROGRAMMABLE POWER MANAGEMENT  
January 2006  
1/110  

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