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PSD813F1V12MT PDF预览

PSD813F1V12MT

更新时间: 2024-10-01 15:48:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 外围集成电路
页数 文件大小 规格书
110页 1018K
描述
PIA-GENERAL PURPOSE, PQFP52, ROHS COMPLIANT, PLASTIC, QFP-52

PSD813F1V12MT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP-52
针数:52Reach Compliance Code:compliant
风险等级:5.62最长访问时间:1.2e-7 ns
JESD-30 代码:S-PQFP-G52JESD-609代码:e4
长度:10 mmI/O 线路数量:27
端口数量:4端子数量:52
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP52,.52SQ封装形状:SQUARE
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
ROM大小(位):1310720 Bits座面最大高度:2.35 mm
最大待机电流:0.0001 A子类别:Other Microprocessor ICs
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED紫外线可擦:N
宽度:10 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

PSD813F1V12MT 数据手册

 浏览型号PSD813F1V12MT的Datasheet PDF文件第2页浏览型号PSD813F1V12MT的Datasheet PDF文件第3页浏览型号PSD813F1V12MT的Datasheet PDF文件第4页浏览型号PSD813F1V12MT的Datasheet PDF文件第5页浏览型号PSD813F1V12MT的Datasheet PDF文件第6页浏览型号PSD813F1V12MT的Datasheet PDF文件第7页 
PSD813F1V  
Flash in-system programmable (ISP) peripherals  
for 8-bit MCUs, 3.3 V  
NOT FOR NEW DESIGN  
FEATURES SUMMARY  
DUAL BANK FLASH MEMORIES  
Figure 1. Packages  
1 Mbit of Primary Flash Memory (8  
Uniform Sectors)  
256 Kbit Secondary EEPROM (4 Uniform  
Sectors)  
Concurrent operation: read from one  
memory while erasing and writing the  
other  
PQFP52 (M)  
16 Kbit SRAM  
PLD WITH MACROCELLS  
Over 3,000 Gates Of PLD: DPLD and  
CPLD  
DPLD - User-defined Internal chip-select  
decoding  
CPLD with 16 Output Macrocells (OMCs)  
and 24 Input Macrocells (IMCs)  
PLCC52 (J)  
TQFQ64 (U)  
27 RECONFIGURABLE I/Os  
27 individually configurable I/O port pins  
that can be used for the following  
functions:  
MCU I/Os;  
PLD I/Os;  
Latched MCU address output; and  
Special function I/Os.  
Note: 16 of the I/O ports may be  
HIGH ENDURANCE:  
configured as open-din outputs.  
100,000 Erase/WRITE Cycles of Flash  
Memory  
ENHANCED JTAG SERIAL PORT  
Built-in JTAG-compliant serial port allows  
full-chip In-System Programmability (ISP)  
Effiient manufacturing allows for easy  
product testing and programming  
10,000 Erase/WRITE Cycles of EEPROM  
1,000 Erase/WRITE Cycles of PLD  
Data Retention: 15-year minimum at 90°C  
(for Main Flash, Boot, PLD and  
Configuration bits).  
PAGE REGISTER  
Internal page register that can be used to  
expand the microcontroller address space  
by a factor of 256.  
SINGLE SUPPLY VOLTAGE:  
3.3V 10ꢀ for PSD813F1V  
STANDBY CURRENT AS LOW AS 50µA  
Packages are ECOPACK  
PROGRAMMABLE POWER MANAGEMENT  
®
October 2008  
Rev 4  
1/110  
This is information on a product still in production but not recommended for new designs.  

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