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PSD813F1V-20M PDF预览

PSD813F1V-20M

更新时间: 2024-10-02 08:34:39
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
110页 899K
描述
PSD813F1V-20M

PSD813F1V-20M 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.84

PSD813F1V-20M 数据手册

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PSD813F1V  
Flash in-system programmable (ISP) peripherals  
for 8-bit MCUs, 3.3 V  
NOT FOR NEW DESIGN  
FEATURES SUMMARY  
DUAL BANK FLASH MEMORIES  
Figure 1. Packages  
1 Mbit of Primary Flash Memory (8  
Uniform Sectors)  
256 Kbit Secondary EEPROM (4 Uniform  
Sectors)  
Concurrent operation: read from one  
memory while erasing and writing the  
other  
PQFP52 (M)  
16 Kbit SRAM  
PLD WITH MACROCELLS  
Over 3,000 Gates Of PLD: DPLD and  
CPLD  
DPLD - User-defined Internal chip-select  
decoding  
CPLD with 16 Output Macrocells (OMCs)  
and 24 Input Macrocells (IMCs)  
PLCC52 (J)  
TQFQ64 (U)  
27 RECONFIGURABLE I/Os  
27 individually configurable I/O port pins  
that can be used for the following  
functions:  
MCU I/Os;  
PLD I/Os;  
Latched MCU address output; and  
Special function I/Os.  
Note: 16 of the I/O ports may be  
HIGH ENDURANCE:  
configured as open-drain outputs.  
100,000 Erase/WRITE Cycles of Flash  
Memory  
ENHANCED JTAG SERIAL PORT  
Built-in JTAG-compliant serial port allows  
full-chip In-System Programmability (ISP)  
Efficient manufacturing allows for easy  
product testing and programming  
10,000 Erase/WRITE Cycles of EEPROM  
1,000 Erase/WRITE Cycles of PLD  
Data Retention: 15-year minimum at 90°C  
(for Main Flash, Boot, PLD and  
Configuration bits).  
PAGE REGISTER  
Internal page register that can be used to  
expand the microcontroller address space  
by a factor of 256.  
SINGLE SUPPLY VOLTAGE:  
3.3V 10ꢀ for PSD813F1V  
STANDBY CURRENT AS LOW AS 50µA  
Packages are ECOPACK  
PROGRAMMABLE POWER MANAGEMENT  
®
October 2008  
Rev 4  
1/110  
This is information on a product still in production but not recommended for new designs.  

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