Overview
— Interfaces to external, memory-mapped serial flash memories
— Supports simultaneous addressing of 2 external serial flashes to achieve up 80 MB/s read bandwidth
RLE decoder supporting memory to memory decoding of RLE data in conjunction with eDMA
Four local interconnect network (LINFlex) controller modules
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— Capable of autonomous message handling (master), autonomous header handling (slave mode), and UART
support
— Compliant with LIN protocol rev 2.1
Three controller-area network (FlexCAN) modules
— Compliant with the CAN protocol version 2.0 C
— 64 configurable buffers
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— Programmable bit rate of up to 1 Mb/s
2
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Four Inter-Integrated Circuit (I C) internal bus controllers with master/slave bus interface
Low-power loop controlled pierce crystal oscillator supporting 4–16MHz external crystal or resonator
Real Time Counter (RTC) with clock source from internal 128 kHz or 16 MHz oscillator supporting autonomous
wake-up with 1 ms resolution with maximum timeout of 2 seconds
— Support for real time counter (RTC) with clock source from external 32 KHz crystal oscillator, supporting
wake-up with 1 s resolution and maximum timeout of one hour
— RTC optionally clocked by fast 4–16 MHz external oscillator
System timers:
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— Four-channel 32-bit System Timer Module (STM)
— Eight-channel 32-bit Periodic Interrupt Timer (PIT) module (including ADC trigger)
— Software Watchdog Timer (SWT)
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System Integration Unit Lite (SIUL) module to manage external interrupts, GPIO and pad control
System Status and Configuration Module (SSCM)
— Provides information for identification of the device, last boot mode, or debug status
— Provides an entry point for the censorship password mechanism
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Clock Generation Module (MC_CGM) to generate system clock sources and provide a unified register interface,
enabling access to all clock sources
Clock Monitor Unit (CMU)
— Monitors the integrity of the fast (4–16 MHz) external crystal oscillator and the primary FMPLL (FMPLL0)
— Acts as a frequency meter, measuring the frequency of one clock source and comparing it to a reference clock
Mode Entry Module (MC_ME)
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— Controls the device power mode, i.e., RUN, HALT, STOP, or STANDBY
— Controls mode transition sequences
— Manages the power control, voltage regulator, clock generation and clock management modules
Power Control Unit (MC_PCU) to implement standby mode entry/exit and control connections to power domains
Reset Generation Module (MC_RGM) to manage reset assertion and release to the device at initial power-up
Nexus Development Interface (NDI) per IEEE-ISTO 5001-2008 Class 3 standard with additional Class 4 features:
— Watchpoint Triggering
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— Processor Overrun Control
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Device/board boundary-scan testing supported per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator controller for regulating the 3.3–5 V supply voltage down to 1.2 V for core logic (requires
external ballast transistor)
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Package:
— 176 LQFP, 0.5 mm pitch, 24 mm 24 mm outline
1. See the device comparison table for package offerings for each device in the family.
PXD20 Microcontroller Data Sheet, Rev. 2
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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