Datasheet > PPXD3015VMM2R

PPXD3015VMM2R

更新时间： 2022-03-22 02:07:24

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
139页	792K
描述
PXS30 Microcontroller

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数据手册

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PPXD3015VMM2R 数据手册

Introduction

Table 1. PXS30 Family Feature Set (continued)

Features

PXS3010

PXS3015

PXS3020

Clocking

Clock monitor unit

(CMU)

3 modules

Clock output

2 modules

Frequency-modulated

phase-locked loop

(FMPLL)

2 modules (system and auxiliary)

IRCOSC – 16 MHz

XOSC 4 MHz – 40 MHz

Supply

Power management unit

(PMU)

Yes

1.2 V low-voltage

detector (LVD12)

1.2 V high-voltage

detector (HVD12)

2.7 V low-voltage

detector (LVD27)

Debug

Nexus

Class 3+ (for cores and SRAM ports)

473 pins

Packages

MAPBGA

257 pins

473 pins

Temperature Ambient

NOTES:

See the T_Arecommended operating condition in the device data sheet

Sphere of Replication.

Does not include Test or Shadow Flash memory space.

Available only on 473-pin package.

DDR available only on 473 package. Other modules available as follows:

EBI or DDR on 473 package.

EBI + PDI on 473 package.

DDR + PDI on 473 package

PDI only on 257 package.

1.3

Block diagram

Figure 1 shows a top-level block diagram of the PXS30 device.

PXS30 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

1 2 345 6 7...139

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