Datasheet > PPXD2020VMG116R

PPXD2020VMG116R

更新时间： 2022-04-07 12:02:34

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
23页	119K
描述
32-bit Power ArchitectureÂ® Dual Core Microcontrollers for Industrial Networking

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数据手册

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PPXD2020VMG116R 数据手册

Features

– In Sleep mode the 32 kHz XTAL can be enabled to run and may be selected to clock the

RTC and API

•

Up to 32 external pins for wake-up from low power modes

Input filters available on all wake-up pins to minimize false wakeups due to noise

Rapid exit from low power mode with fast startup internal voltage regulator

2.5

Packages

PXN20 family members are offered in the following package types:

•

208-ball MAPBGA, 1mm ball pitch, 17mm  17mm outline for production

256-ball MAPBGA 1mm ball pitch 17mm  17mm outline for emulation, providing access to full

Nexus port without sacrificing GPIO functionality (not available for production)

2.6

Module Features

The following sections provide details of the modules implemented on the PXN20 family.

2.6.1

High Performance e200z650 Core Processor (CPU)

32-bit CPU built on Power Architecture technology

•

Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction

Thirty-two 64-bit general-purpose registers (GPRs)

Memory management unit (MMU) with 32-entry fully-associative translation look-aside buffer

(TLB)

•

Branch processing unit

Fully pipelined load/store unit

32 KB unified cache with line locking

— 4/8-way set associative

— Two 32-bit fetches per clock

— Eight-entry store buffer

— Way locking

— Supports assigning cache as instruction or data only on a per way basis

— Supports tag and data parity

Vectored interrupt support

•

Very low interrupt latency

Reservation instructions for implementing read-modify-write constructs (internal SRAM and

flash)

•

Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit general

purpose registers

Floating point

PXN20 Product Brief, Rev. 1

Freescale Semiconductor

1...4 5 678 9 10...23

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