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PPG33F-50M PDF预览

PPG33F-50M

更新时间： 2024-11-23 10:06:19
品牌 Logo 应用领域
DATADELAY 逻辑集成电路脉冲光电二极管脉冲发生器
页数 文件大小 规格书
5页 285K
描述
3-BIT PROGRAMMABLE PULSE GENERATOR (SERIES PPG33F)

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中文翻译

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PPG33F-50M 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.67Is Samacsys：N
JESD-30 代码：R-PDIP-T14逻辑集成电路类型：LOGIC CIRCUIT
功能数量：1端子数量：14
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：8.255 mm标称供电电压 (Vsup)：5 V
表面贴装：NO端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

PPG33F-50M 数据手册

 浏览型号PPG33F-50M的Datasheet PDF文件第2页浏览型号PPG33F-50M的Datasheet PDF文件第3页浏览型号PPG33F-50M的Datasheet PDF文件第4页浏览型号PPG33F-50M的Datasheet PDF文件第5页 
PPG33F  
3-BIT PROGRAMMABLE  
PULSE GENERATOR  
(SERIES PPG33F)  
FEATURES  
PACKAGES  
•
•
•
•
•
•
•
•
•
Digitally programmable in 7 steps  
Monotonic pulse-width-vs-address variation  
Rising edge triggered  
16  
15  
14  
13  
12  
11  
10  
9
VCC  
OUT/  
N/C  
N/C  
A0  
A1  
A2  
N/C  
TRIG  
1
2
3
4
5
6
7
8
TRIG  
OUT  
N/C  
N/C  
N/C  
14  
13  
12  
11  
10  
9
VCC  
1
2
3
4
5
6
7
N/C  
OUT  
N/C  
N/C  
N/C  
OUT/  
N/C  
N/C  
A0  
A1  
A2  
Two separate outputs: inverting & non-inverting  
Precise and stable pulse width  
Input & outputs fully TTL interfaced & buffered  
10 T2L fan-out capability  
RES  
GND  
RES  
GND  
8
Fits standard 14-pin DIP socket  
Auto-insertable  
DIP  
Gull-Wing  
PPG33F-xx Commercial  
PPG33F-xxM Military  
PPG33F-xxC3 Commercial  
PPG33F-xxMC3 Military  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The PPG33F-series device is a 3-bit digitally programmable pulse  
generator. The width, PWA, depends on the address code (A2-A0)  
according to the following formula:  
TRIG Trigger Input  
OUT Non-inverted Output  
OUT/ Inverted Output  
A0-A2 Address Bits  
PWA = PW0 + TINC * A  
RES  
Reset  
VCC +5 Volts  
GND Ground  
where A is the address code, TINC is the incremental pulse width of the  
device, and PW0 is the inherent pulse width of the device. The  
incremental width is specified by the dash number of the device and can range from 0.5ns through 50ns,  
inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are  
forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The  
address is not latched and must remain asserted while the output pulse is active.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
•
Programmed pulse width tolerance: 5% or 1ns,  
Part  
Incremental Width  
Per Step (ns)  
0.5 ± 0.3  
1 ± 0.4  
Total Width  
Change (ns)  
3.50 ± 1.00  
7.00 ± 1.00  
14.0 ± 1.00  
21.0 ± 1.05  
28.0 ± 1.40  
35.0 ± 1.75  
42.0 ± 2.10  
56.0 ± 2.80  
70.0 ± 3.50  
140 ± 7.00  
210 ± 10.5  
280 ± 14.0  
350 ± 17.5  
whichever is greater  
Number  
PPG33F-.5  
PPG33F-1  
PPG33F-2  
PPG33F-3  
PPG33F-4  
PPG33F-5  
PPG33F-6  
PPG33F-8  
PPG33F-10  
PPG33F-20  
PPG33F-30  
PPG33F-40  
PPG33F-50  
•
•
•
•
•
Inherent width (PW0): 9ns typical  
Inherent delay (TTO): 3.5ns ± 2ns  
Operating temperature: 0° to 70° C  
Supply voltage VCC: 5VDC ± 5%  
2 ± 0.4  
3 ± 0.5  
4 ± 0.5  
Supply current:  
ICC = 41ma typical  
5 ± 0.6  
6 ± 0.7  
8 ± 0.8  
10 ± 1.0  
20 ± 1.5  
30 ± 1.8  
40 ± 2.0  
50 ± 2.5  
1997 Data Delay Devices  
NOTE: Any dash number between .5 and 50 not  
shown is also available.  
Doc #97010  
1/15/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
12345

中文翻译

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