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PPG312F-20MC5 PDF预览

PPG312F-20MC5

更新时间： 2024-11-09 20:17:19
品牌 Logo 应用领域
DATADELAY 光电二极管逻辑集成电路
页数 文件大小 规格书
5页 45K
描述
Logic Circuit, PDSO40

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中文翻译

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PPG312F-20MC5 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：SOP,
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.67JESD-30 代码：R-PDSO-G40
JESD-609代码：e3长度：52.832 mm
逻辑集成电路类型：LOGIC CIRCUIT功能数量：1
端子数量：40封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：8.128 mm
标称供电电压 (Vsup)：5 V表面贴装：YES
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

PPG312F-20MC5 数据手册

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PPG312F  
Ò
12-BIT PROGRAMMABLE  
PULSE GENERATOR  
(SERIES PPG312F)  
data  
delay  
3
devices, inc.  
FEATURES  
PACKAGES  
TRIG  
N/C  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
N/C  
N/C  
GND  
A3  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
VCC  
N/C  
OUT  
OUT/  
N/C  
RES  
N/C  
N/C  
VCC  
A0  
2
·
·
·
·
·
·
·
·
·
Digitally programmable in 4096 steps  
Monotonic pulse-width-vs-address variation  
Rising edge triggered  
Two separate outputs: inverting & non-inverting  
Precise and stable pulse width  
Input & outputs fully TTL interfaced & buffered  
10 T2L fan-out capability  
3
4
PPG312F-xx  
DIP  
PPG312F-xxC5  
Gull-Wing  
PPG312F-xxM  
Military DIP  
PPG312F-xxMC5  
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
A1  
A2  
Fits standard 40-pin DIP socket  
Auto-insertable  
A5  
N/C  
N/C  
N/C  
N/C  
N/C  
A4  
Military Gull-Wing  
A6  
A7  
GND  
A8  
A9  
A10  
A11  
N/C  
VCC  
PIN DESCRIPTIONS  
FUNCTIONAL DESCRIPTION  
TRIG Trigger Input  
The PPG312F-series device is a 12-bit digitally programmable pulse  
generator. The width, PWA, depends on the address code (A11-A0)  
according to the following formula:  
OUT Non-inverted Output  
OUT/ Inverted Output  
A0-A11 Address Bits  
RES  
VCC +5 Volts  
GND Ground  
Reset  
PWA = PW0 + TINC * A  
where A is the address code, TINC is the incremental pulse width of the  
device, and PW0 is the inherent pulse width of the device. The  
incremental width is specified by the dash number of the device and can range from 0.5ns through 400ns,  
inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are  
forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The  
address is not latched and must remain asserted while the output pulse is active.  
DASH NUMBER SPECIFICATIONS  
SERIES SPECIFICATIONS  
Part  
Number  
Incremental Width  
Per Step (ns)  
.5 ± .3  
Total Width  
Change (us)  
2.048 ± 0.10  
4.096 ± 0.20  
8.192 ± 0.41  
20.48 ± 1.02  
40.96 ± 2.05  
81.92 ± 4.10  
204.8 ± 10.2  
409.6 ± 20.5  
819.2 ± 41.0  
1,638.4 ± 81.9  
·
Programmed pulse width tolerance: 5% or 2ns,  
whichever is greater  
PPG312F-.5  
PPG312F-1  
PPG312F-2  
PPG312F-5  
PPG312F-10  
PPG312F-20  
PPG312F-50  
PPG312F-100  
PPG312F-200  
PPG312F-400  
·
·
·
·
·
Inherent width (PW0):20ns typical  
Inherent delay (TTO): 10ns ± 2ns  
Operating temperature: 0° to 70° C  
Supply voltage VCC: 5VDC ± 5%  
Supply current: ICC = 200ma typical  
1 ± .5  
2 ± .5  
5 ± 1.5  
10 ± 2.0  
20 ± 2.0  
50 ± 2.5  
100 ± 5.0  
200 ± 10.0  
400 ± 20.0  
NOTE: Any dash number between .5 and 400 not  
shown is also available.  
Ó1997 Data Delay Devices  
Doc #97008  
1/15/97  
DATA DELAY DEVICES, INC.  
3 Mt. Prospect Ave. Clifton, NJ 07013  
1
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