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PPC440SP-3FB533C PDF预览

PPC440SP-3FB533C

更新时间: 2024-01-03 13:54:31
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AMCC /
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83页 1159K
描述
Microprocessor

PPC440SP-3FB533C 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:compliant风险等级:5.7
Base Number Matches:1

PPC440SP-3FB533C 数据手册

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Part Number 440SP  
Revision 1.11 - July 12, 2005  
Preliminary Data Sheet  
PowerPC 440SP Embedded Processor  
Features  
• PowerPC440 processor core operating at up to  
667MHz with 32-KB I- and D-caches (with parity  
checking)  
• I2O Messaging Unit with two DMA controllers  
• External Peripheral Bus (24-bit Address, 8-bit  
Data) for up to three devices  
• On-chip 256-KB SRAM configurable as L2 Cache  
or Ethernet Packet/Code store memory  
• One Ethernet 10/100/1000 Mbps half- or full-  
duplex interface. Operational modes supported  
are MII and GMII.  
• Selectable Processor:Bus clock ratios (Refer to  
the Clocking chapter in the PPC440SP Embedded  
Processor User’s Manual for details)  
• Programmable Interrupt Controller supports  
interrupts from a variety of sources.  
• Supports up to 4 GB (2 Chip Selects) of 64-bit/32-  
bit SDRAM with ECC  
• Programmable General Purpose Timers (GPT)  
• Three serial ports (16750 compatible UART)  
• Two IIC interfaces  
– DDR1 266-333-400  
– DDR2 400-533-667  
• Three DDR PCI-X interfaces (32-bit or 64-bit) up  
to 133 MHz (DDR 266) with support for  
conventional PCI  
• General Purpose I/O (GPIO) interface available  
• JTAG interface for board level testing  
• Processor can boot from PCI memory  
• XOR Accelerator with DMA controller  
Description  
Designed specifically to address high-end embedded  
applications for storage, the PowerPC 440SP  
Embedded Processor (PPC440SP) provides a high-  
performance, low power solution that interfaces to a  
wide range of peripherals by incorporating on-chip  
power management features and lower power  
dissipation.  
Technology: CMOS Cu-11, 0.13mm, 7-layer metal  
Package: 29mm, 783-ball, 1mm pitch, Flip Chip-  
Plastic Ball Grid Array (FC-PBGA)  
Power (estimated): Less than 6W @533MHz  
Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5V  
This chip contains a high-performance RISC  
processor core, a DDR2 SDRAM controller,  
configurable 256KB SRAM to be used as L2 cache or  
software-controlled on-chip memory, three DDR PCI-X  
bus interfaces, an Ethernet interface, an I2O/DMA  
controller, control for external ROM and peripherals,  
an XOR DMA unit, serial ports, IIC interfaces, and  
general purpose I/O.  
AMCC Proprietary  
1

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RISC Microprocessor, 32-Bit, 800MHz, CMOS, PBGA675, 27 X 27 MM, 1 MM PITCH, PLASTIC, FCBGA