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PM8536B-FEI PDF预览

PM8536B-FEI

更新时间: 2024-02-03 23:01:52
品牌 Logo 应用领域
美国微芯 - MICROCHIP 接口集成电路
页数 文件大小 规格书
2页 1172K
描述
Interface Circuit

PM8536B-FEI 技术参数

生命周期:Active包装说明:,
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:2.04接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:S-XXSS-X功能数量:1
最高工作温度:105 °C最低工作温度:
封装主体材料:UNSPECIFIED封装形状:SQUARE
封装形式:SPECIAL SHAPE表面贴装:NO
温度等级:OTHER端子形式:UNSPECIFIED
端子位置:UNSPECIFIEDBase Number Matches:1

PM8536B-FEI 数据手册

 浏览型号PM8536B-FEI的Datasheet PDF文件第2页 
Switchtec™ PCIe® Switches  
Switchtec™ PFX/PFX-I PCIe® Gen3 Fanout Switch Families  
PM853x PFX and PM857x PFX-I 96/80/64/48/32/24xG3 PCIe Gen3 Fanout Switches  
Summary  
The Switchtec PFX/PFX-I PCIe Gen3 fanout switch families comprise high reliabil-  
ity PCIe Base Specification 3.1-compliant switches supporting up to 96 lanes, 24  
virtual switch partitions, 48 Non-Transparent Bridges (NTBs), hot- and surprise-  
plug controllers for each port, advanced error containment and comprehensive  
diagnostics and debug capabilities. The PFX-I Gen3 PCIe Switch supports the  
full feature set available on the PFX* and operates over an extended industrial  
temperature range of –40°C ambient to 105°C junction.  
Typical applications include data center equipment, defense, industrial servers,  
workstations, test equipment, video production and broadcasting equipment,  
cellular infrastructure, access networks, metro networks and core networking.  
Features  
High-Performance Non-Blocking Switches  
PCIe Interfaces  
Up to 174 GB/s switching capacity  
96-lane, 80-lane, 64-lane, 48-lane, 32-lane, and 24-lane  
variants  
Passive, managed and optical cables  
SFF-8644, SFF-8643, SFF-8639, OCuLink and other  
connectors  
Ports bifurcate from x2 to x16 lanes  
Up to 48 NTBs assignable to any port  
Logical Non-Transparent (NT) interconnect allows for larger  
topologies (up to 256 masters)  
Supports 1+1 and N+1 failover mechanisms  
NT address translation using direct windows and multiple  
sub-windows per BAR  
SHPC-enabled slot and edge connectors  
Diagnostics and Debug  
Transaction Layer Packet (TLP) generator for testing and  
debugging of links and error handling  
Real-time eye capture  
Any-to-any port mirroring for debug purposes  
External loopback at PHY and TLP layers  
Errors, statistics, performance, and TLP latency counters  
Supports multicast groups per port  
PFX-I supports an extended industrial temperature range  
T : –40°C to T : 105°C  
A
J
Error Containment  
Advanced Error Reporting (AER) on all ports  
Downstream Port Containment (DPC) on all downstream  
ports  
Poisoned TLP blocking  
Completion Timeout Synthesis (CTS) to prevent an error  
state in an upstream host due to incomplete non-posted  
transactions  
Hot- and surprise-plug controllers per port  
GPIOs configurable for different cable/connector standards  
*Except for Adaptive Voltage Scaling (AVS)  
www.microchip.com  

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