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PM4341A PDF预览

PM4341A

更新时间: 2024-11-11 22:26:27
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2页 45K
描述
T1 TRANSCEIVER

PM4341A 数据手册

 浏览型号PM4341A的Datasheet PDF文件第2页 
PM4341A  
Summary Information  
T1XC  
T1TRANSCEIVER  
TRANSMITSECTION  
RECEIVE SECTION  
• Provides loss of signal, red alarm,  
yellow alarm and AIS alarm  
indication. Detects violations of the  
ANSI T1.403 12.5% pulse density  
rule over a moving 192 bit window.  
FEATURES  
• Monolithic single chip device which  
integrates a full featured T1 framer  
with an on-chip analog line interface.  
• Provides per channel minimum ones  
density through Bell (Bit 7), GTE or  
DDS zero code suppression.  
• Detects violations of the ANSI T1.403  
12.5% pulse density rule over a  
moving 192 bit window.  
• Supports SF, ESF, T1DM (DDS) and  
SLC®96 format DS1 signals.  
Supports unframed mode. Supports  
B8ZS or AMI line codes.  
• Supports line and path performance  
monitoring per Bellcore, AT&T and  
ANSI recommendations.  
• Inserts the data link in ESF, T1DM  
and SLC®96 formats. Inserts the D-  
channel for primary rate interfaces.  
• Recovers clock and data from the  
incoming DSX-1 signal, generates  
DSX-1 output signal.  
• Accumulators are provided for ESF  
CRC-6 and framing bit errors, Line  
Code Violations and Loss Of Frame  
or Change Of Frame Alignment  
events.  
• Generates AIS and yellow alarm in  
all formats.  
• Supports transfer of PCM and  
signalling to/from 1.544 Mbit/s and  
2.048 Mbit/s backplane buses.  
Supports gapped data streams used  
in higher rate multiplexing.  
• Inserts the data link in ESF, T1DM  
and SLC®96 formats. Inserts the D-  
channel for primary rate interfaces.  
• Extracts the data link in ESF, T1DM  
and SLC®96 formats. Extracts the  
D-channel for primary rate interfaces.  
• Generates ESF bit-oriented codes  
and provides an HDLC interface for  
generating the ESF datalink.  
• Provides robbed bit signalling  
insertion/extraction, idle code  
substitution, digital milliwatt code  
substitution, data inversion and 2  
superframes of signalling debounce  
on a per channel basis.  
• Provides ESF bit-oriented code  
detection and an HDLC interface for  
terminating the ESF datalink.  
• Inserts programmable in-band  
loopback codes.  
• Provides a 2 frame elastic store for  
jitter and wander attenuation.  
• Provides a FIFO buffer for jitter  
attenuation and rate conversion.  
• Pin compatible with the PM6341  
E1XC E1 Transceiver.  
• Detects programmable in-band  
loopback codes.  
• Software compatible with the  
PM4344 TQUAD Quad T1 Framer  
and PM4388 TOCTL Octal T1  
Framer.  
BLOCK DIAGRAM  
TCLKI  
TRANSMITTER  
TOPS  
TIMING OPTIONS  
BTIF  
BACK-  
PLANE  
TRANSMIT  
INTER-  
FACE  
XBAS  
BTPCM/BTDP  
BTSIG/BTDN  
BASICTRANSMITTER:  
FRAME GENERATION,  
ALARM INSERTION,  
TRUNK CONDITIONING  
LINE CODING  
• Provides an 8-bit microprocessor bus  
interface for configuration, control  
and status monitoring.  
TAP  
BTFP  
XPLS  
DJAT  
ANALOG DSX-1  
DIGITAL JITTER  
BTCLK  
PULSE  
ATTENUATOR  
GENERATOR  
TAN  
• Low-power 5V CMOS technology.  
TPSC  
PER-CHAN  
CONT:  
SIG,IDLE,  
ZERO CONT  
XIBC  
IN-BAND  
LOOPBACK  
CODE  
TC  
• Avalable in a high density 80-pin (14  
by14mm) PQFP or in a 68-pin PLCC  
package.  
GENERATOR  
DTIF  
TCLKO  
DIGITAL DS-1  
TRANSMIT  
INTERFACE  
TDP/TDD  
A(7-0)  
RDB  
XPDE  
PULSE  
DENSITY  
ENFORCER  
TDN/TFLG  
MPIF  
MICRO-  
PROCESS-  
OR  
WRB  
CSB  
ALE  
APPLICATIONS  
• T1 & T3 Multiplexers  
• T1 Frame Relay Interfaces  
• T1 ATM UNI Interfaces  
• Fractional T1  
INTERFACE  
XBOC  
BIT-  
ORIENTED  
CODE GEN.  
TDLCLK/  
TDLUDR  
XFDL  
HDLC  
TRANS-  
MITTER  
INTB  
TDLSIG/  
TDLINT  
RSTB  
D(7-0)  
BRCLK  
RECEIVER  
• T1 Channel Service Units (CSUs)  
and Data Service Units (DSUs)  
BRFPI  
XCLK/VCLK  
PMON  
PER-  
FORMANCE  
MONITOR  
COUNTERS  
BRPCM/BRDP  
BRSIG/BRDN  
SIGX  
ELST  
ELASTIC  
STORE  
RAS  
REF  
RRC  
RSLC  
ANALOG  
DSX-1 PULSE  
SLICER  
• Digital Access and Cross-Connect  
Systems (DACS) and Electronic  
Digital Cross-Connects (EDSX)  
SIGNALLING  
EXTRACT-  
OR  
BRIF  
BACK-  
PLANE  
RECEIVE  
INTER-  
FACE  
BRFPO  
FRM R  
FRAMER:  
FRAME  
RDPCM/RPCM  
RCLKO  
RCLKI  
DRIF  
DIGITAL  
DS-1 RX  
INTER-  
FACE  
• Digital Loop Carriers (DLCs)  
CDRC  
CLOCK AND  
DATA  
RFP  
ALIGNMENT,  
ALARM  
RDP/RDD/  
SDP  
• SONET Add-Drop Multiplexers  
(ADM)  
EXTRACT  
RECOVERY  
RPSC  
PER-CHANNEL  
CONTROL:  
TRUNK  
RDN/RLCV/  
SDN  
FRAM  
FRAMER/  
SLIP BUFFER  
RAM  
IBCD  
ALM I  
ALARM  
INTE-  
IN-BAND  
LOOPBACK  
CODE  
• ISDN Primary Rate Interfaces (PRI)  
CONDITION  
GRATOR  
• Digital Private Branch Exchanges  
(PBX)  
DETECTOR  
PDVD  
PULSE  
DENSITY  
VIOLATION  
DETECTOR  
RBOC  
BIT-  
ORIENTED  
CODE  
RDLSIG/  
RDLINT  
RFDL  
HDLC  
RECEIVER  
• T1 & T3 Test Equipment  
RDLCLK/  
RDLEOM  
DETECTOR  
SLC®96isaregisteredtrademarkofAT&T  
PMC-920108(R7)  
© 1998 PMC-Sierra, Inc. March, 1998  

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