AM3874, AM3872, AM3871
www.ti.com
SPRS695–SEPTEMBER 2011
AM387x Sitara™
ARM® Microprocessors (MPUs)
Check for Samples: AM3874, AM3872, AM3871
1 High-Performance System-on-Chip (SoC)
1.1 Features
12
8-bit SD Capture Ports
• High-Performance Sitara™ ARM®
Microprocessors (MPUs)
– Up to 1-GHz ARM® Cortex™-A8 RISC MPU
• ARM® Cortex™-A8 Core
•
•
One 8/16/24-bit Input
One 8-bit Only Input
– Two 165 MHz HD Video Display Outputs
One 16/24/30-bit and one 16/24-bit Output
– ARMv7 Architecture
•
•
In-Order, Dual-Issue, Superscalar
Microprocessor Core
– Composite or S-Video Analog Output
– MacroVision® Support Available
•
•
•
NEON™ Multimedia Architecture
Supports Integer and Floating Point
Jazelle® RCT Execution Environment
– Digital HDMI 1.3 transmitter With Integrated
PHY
– Advanced Video Processing Features Such
as Scan/Format/Rate Conversion
– Three Graphics Layers and Compositors
• Dual 32-bit LPDDR/DDR2/DDR3 SDRAM
• ARM® Cortex™-A8 Memory Architecture
– 32K-Byte Instruction and Data Caches
– 512K-Byte L2 Cache
– 64K-Byte RAM, 48K-Byte Boot ROM
• 128K-Bytes On-Chip Memory Controller
(OCMC) RAM
• Imaging Subsystem (ISS)
– Camera Sensor Connection
Interfaces
– Supports up to LPDDR-400, DDR2-800, and
DDR3-800
– Up to Eight x 8 Devices Total 2 GB Total
Address Space
– Dynamic Memory Manager (DMM)
•
Parallel Connection for Raw (up to 16-Bit)
and BT.656/BT.1120 (8-/16-bit)
•
Programmable Multi-Zone Memory
Mapping and Interleaving
– Image Sensor Interface (ISIF) for Handling
Image/Video Data From the Camera Sensor
– Resizer
•
•
Enables Efficient 2D Block Accesses
Supports Tiled Objects in 0°, 90°, 180°, or
270° Orientation and Mirroring
•
•
Resizing Image/Video From 1/16x to 8x
Generating Two Different Resizing
Outputs Concurrently
•
Optimizes Interlaced Accesses
• General Purpose Memory Controller (GPMC)
– 8-/16-bit Multiplexed Address/Data Bus
• Media Controller
– 512M-Byte Total Address Space Divided
– Controls the HDVPSS and ISS
• SGX530 3D Graphics Engine
– Delivers up to 18 MPoly/sec
– Universal Scalable Shader Engine
Among up to 8 Chip Selects
– Glueless Interface to NOR Flash, NAND
Flash (BCH/Hamming Error Code Detection),
SRAM and Pseudo-SRAM
– Error Locator Module (ELM) Outside of
GPMC to Provide Upto 16-Bit/512-Bytes
Hardware ECC for NAND
– Direct3D Mobile, OpenGLES 1.1 and 2.0,
OpenVG 1.0, OpenMax API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
• Endianness
– Flexible Asynchronous Protocol Control for
Interface to FPGA, CPLD, ASICs, etc.
– ARM Instructions/Data – Little Endian
• HD Video Processing Subsystem (HDVPSS)
– Two 165 MHz HD Video Capture Inputs
• Enhanced Direct-Memory-Access (EDMA)
Controller
– Four Transfer Controllers
– 64/8 Independent DMA/QDMA Channels
•
One 16/24-bit Input, Splittable into Dual
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Copyright © 2011, Texas Instruments Incorporated