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PLL701-31SCL PDF预览

PLL701-31SCL

更新时间: 2024-11-09 10:08:27
品牌 Logo 应用领域
PLL 时钟
页数 文件大小 规格书
5页 201K
描述
Low EMI Spread Spectrum Multiplier Clock

PLL701-31SCL 数据手册

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PLL701-31  
Low EMI Spread Spectrum Multiplier Clock  
FEATURE  
PIN CONFIGURATION  
Spread Spectrum Clock Generator with 1x  
outputs.  
XIN/FIN  
XOUT/SD*^  
SC0^  
VDD  
1
2
3
4
8
7
6
5
Output frequency ranges: 10MHz to 30MHz.  
Accepts input from crystal or reference clock.  
Selectable Center, Down or Asymmetric Spread  
Modulation.  
SC2^  
FOUT  
GND  
SC1^  
Selectable Modulation magnitude.  
TTL/CMOS compatible outputs.  
3.0V (+/-10%) Supply Voltage.  
Low short-term jitter.  
XIN/FIN = 10 ~ 30 MHz  
Note: ^: Internal pull-up resistor (120kfor SD, 30 kfor  
SC0-SC2).  
Available in 8-Pin 150mil SOIC.  
*: The value of SD is latched upon power-up. The  
internal pull-up resistor results in a default high value  
when no pull-down resistor is connected to this pin  
(recommended external pull-down resistor of 27 k).  
DESCRIPTION  
The PLL701-31 is a Spread Spectrum Clock  
Generator designed to reduce EMI in high-speed  
digital systems. The device is designed to operate  
from a crystal or reference clock input and provides a  
1x modulated clock output. Center, Down and  
Asymmetric spread types are selectable as well as  
the modulation magnitude.  
OUTPUT CLOCK SELECTION  
SST Modulation  
SD  
SC2  
SC1  
SC0  
Magnitude  
Freq.  
Type  
-3.75%  
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
1
3.75%  
3.50%  
3.75%  
3.25%  
3.50%  
3.75%  
3.25%  
3.50%  
3.75%  
0.00%  
D
D
A
D
A
A
C
C
C
-3.50%  
+0.125%, -3.625%  
-3.25%  
+0.125%, -3.375%  
+0.25%, -3.5%  
+/-1.625 %  
Fin / 512  
+/-1.75%  
+/-1.875%  
SST OFF  
Notes: A: Asymmetric Spread. D: Down Spread. C: Center Spread.  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991  
www.phaselink.com  
Rev 11/28/05 Page 1  

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