Datasheet > PL585-P8-168OC-R

PL585-P8-168OC-R

更新时间： 2024-11-01 22:50:27

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
7页	422K
描述
IC CLK BUFFER LVPECL 16TSSOP

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数据手册

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PL585-P8-168OC-R 数据手册

(Preliminary) PL585-XX

19MHz to 800MHz Low Phase-Noise VCXO

PIN CONFIGURATION

FEATURES



< 0.5ps RMS phase jitter (12kHz to 20MHz)

at 622.08MHz (LVPECL/LVDS)

30ps max peak to peak period jitter

Ultra Low-Power Consumption



XIN

VCON

XOUT

VDDANA

VDDDIG

VDDBUF



< 90mA @622MHz PECL output

<10A at Power Down (PDB) Mode

Input Frequency:



DNC



Fundamental Crystal: 19MHz to 44MHz

Output Frequency:

19MHz to 800MHz output.

OE/PDB

DNC



Output types: LVPECL, LVDS, or LVCMOS.

High Linearity VCXO: <10% linearity

Pullability: ±150 ppm

Programmable OE input polarity,

о Programmable Hi-Z or Active Low disabled

state (CMOS output only)

GNDANA

GNDDIG

GNDBUF

VDDBUF

DNC

TSSOP-16L



Power Supply: 3.3V, ±10%

Operating Temperature Ranges:

 Commercial: 0C to 70C

 Industrial: -40C to 85C

Available in TSSOP package



OUTPUT ENABLE CONTROL

DESCRIPTION

OE Options

(Programmable)

Conventional

Polarity

The PL585 is a Dual LC core monolithic IC VCXO,

capable of maintaining sub-picoseconds RMS phase

jitter, while covering a wide frequency output range

up to 800MHz, without the use of external

components. The high performance and high

frequency output is achieved using a low cost

fundamental crystal of between 19MHz and 44 MHz.

The PL585 is designed to address the demanding

requirements of high performance applications such

Fiber Channel, serial ATA, Ethernet, SAN,

SONET/SDH, etc.

State

0 (Default)

Output enabled

Tri-state

Output enabled

Reverse

Polarity

1 (Default)

BLOCK DIAGRAM

OE/PDB

XIN/REF

XOUT

Xtal

Osc

LF – HF

LCVCOs

PD/CP

Pre-scalar

Varicap

VCON

M Divider

P Divider

Programmable Function

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 11/18/11 Page 1

12 3 4 5 6 7

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