Datasheet > PL102-10

PL102-10

更新时间： 2023-12-06 19:51:50

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
16页	1644K
描述
The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute

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数据手册

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PL102-10 数据手册

PL102-10

Low Skew Output Buffer

Features

General Description

• Frequency Range:

The PL102-10 is a high performance, low skew, low

jitter zero delay buffer designed to distribute high speed

clocks and is available in 8-lead SOIC or 6-lead SOT23

package. It has two outputs that are synchronized with

the input. The synchronization is established via

CLKOUT feed back to the input of the PLL. Because

the skew between the input and output is less than

±350 ps, the device acts as a zero delay buffer.

- 15 MHz to 170 MHz @ 3.3V

- 15 MHz to 145 MHz @ 2.5V

• Internal Phase Locked Loop Allows Spread

Spectrum Modulation on Reference Clock to Pass

to Outputs

• Zero Input-to-Output Delay

• Less than 700 ps Device-to-Device Skew

• Less than 200 ps Skew between Outputs

• Less than 100 ps Cycle-to-Cycle Jitter

• 2.5V or 3.3V Power Supply

• Available in 8-Lead SOIC or 6-Lead SOT23

GREEN/RoHS-Compliant Packages

Package Types

PL102-10

6-Lead SOT23 (T)

(Top View)

PL102-10

8-Lead SOIC (S)

(Top View)

REFIN

GND

CLKOUT

DNC

CLK1

GND

CLK2

VDD

CLK1

CLK2

DNC

REFIN

CLKOUT

VDD

Block Diagram

REFIN

CLKOUT

CLK1

PLL

CLK2

 2020 Microchip Technology Inc.

DS20006345A-page 1

12 3 4 5 6 7...16

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