Datasheet > PL102-10SC

PL102-10SC

更新时间： 2024-01-16 14:55:13

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
7页	287K
描述
Low Skew Output Buffer

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数据手册

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PL102-10SC 数据手册

PL102-10

Low Skew Output Buffer

FEATURES

PIN CONFIGURATION

 Frequency Range:

− 15 to 170MHz @ 3.3V

− 15 to 145MHz @ 2.5V

 Internal Phase Locked Loop Allows Spread

Spectrum Modulation on Reference Clock to

Pass to Outputs.

REFIN

GND

CLKOUT

DNC

CLK1

CLK2

DNC

 Zero Input to Output Delay

 Less Than 700ps Device to Device Skew

 Less Than 200ps Skew Between Outputs

 Less Than 100ps Cycle to Cycle Jitter

 2.5V or 3.3V Power Supply

VDD

SOP-8L

 Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS

Compliant Packages

CLK1

CLK2

GND

VDD

REFIN

CLKOUT

SOT23-6L

DESCRIPTION

The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed

clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the

input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between

the input and output is less than 350 ps, the device acts as a zero delay buffer.

BLOCK DIAGRAM

REFIN

CLKOUT

CLK1

PLL

CLK2

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 1

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