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PKD01BIEY

更新时间： 2024-02-16 13:53:40
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
18页 398K
描述
IC SPECIALTY ANALOG CIRCUIT, CDIP14, CERDIP-14, Analog IC:Other

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中文翻译

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PKD01BIEY 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：HERMETIC SEALED, DIP-14Reach Compliance Code：unknown
风险等级：5.64模拟集成电路 - 其他类型：ANALOG CIRCUIT
JESD-30 代码：R-GDIP-T14JESD-609代码：e0
标称负供电电压 (Vsup)：-15 V功能数量：1
端子数量：14最高工作温度：85 °C
最低工作温度：-25 °C封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP14,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：+-15 V
认证状态：Not Qualified子类别：Other Analog ICs
标称供电电压 (Vsup)：15 V表面贴装：NO
温度等级：OTHER端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

PKD01BIEY 数据手册

 浏览型号PKD01BIEY的Datasheet PDF文件第2页浏览型号PKD01BIEY的Datasheet PDF文件第3页浏览型号PKD01BIEY的Datasheet PDF文件第4页浏览型号PKD01BIEY的Datasheet PDF文件第5页浏览型号PKD01BIEY的Datasheet PDF文件第6页浏览型号PKD01BIEY的Datasheet PDF文件第7页 
Monolithic Peak Detector  
with Reset-and-Hold Mode  
a
PKD01  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Monolithic Design for Reliability and Low Cost  
High Slew Rate: 0.5 V/␮s  
+IN –IN  
OUTPUT V+  
V–  
Low Droop Rate  
TA = 25؇C: 0.1 mV/ms  
TA = 125؇C: 10 mV/ms  
–
Low Zero-Scale Error: 4 mV  
Digitally Selected Hold and Reset Modes  
Reset to Positive or Negative Voltage Levels  
Logic Signals TTL and CMOS Compatible  
Uncommitted Comparator On-Chip  
Available in Die Form  
CMP  
+
LOGIC  
GND  
V–  
OUTPUT  
BUFFER  
DET  
GATED  
"g  
–
C
+
"
D
m
1
OUTPUT  
–
A
+
–IN  
+IN  
AMP  
GATED  
"g  
AMP  
"
m
–
–IN  
+IN  
B
+
PKD01  
GENERAL DESCRIPTION  
RST  
The PKD01 tracks an analog input signal until a maximum  
amplitude is reached. The maximum value is then retained as a  
peak voltage on a hold capacitor. Being a monolithic circuit, the  
PKD01 offers significant performance and package density  
advantages over hybrid modules and discrete designs without  
sacrificing system versatility. The matching characteristics  
attained in a monolithic circuit provide inherent advantages  
when charge injection and droop rate error reduction are  
primary goals.  
RST DET OPERATIONAL MODE  
C
H
0
0
1
1
0
1
1
0
PEAK DETECT  
PEAK HOLD  
RESET  
SWITCHES SHOWN FOR:  
RST = “0,” DET = “0”  
INDETERMINATE  
The output buffer amplifier features an FET input stage to  
reduce droop rate error during lengthy peak hold periods. A bias  
current cancellation circuit minimizes droop error at high ambi-  
ent temperatures.  
Innovative design techniques maximize the advantages of mono-  
lithic technology. Transconductance (gm) amplifiers were chosen  
over conventional voltage amplifier circuit building blocks. The  
gm amplifiers simplify internal frequency compensation, minimize  
acquisition time and maximize circuit accuracy. Their outputs  
are easily switched by low glitch current steering circuits. The  
steered outputs are clamped to reduce charge injection errors  
upon entering the hold mode or exiting the reset mode. The inher-  
ently low zero-scale error is further reduced by active Zener-Zap  
trimming to optimize overall accuracy.  
Through the DET control pin, new peaks may either be detected  
or ignored. Detected peaks are presented as positive output  
levels. Positive or negative peaks may be detected without  
additional active circuits, since Amplifier A can operate as an  
inverting or noninverting gain stage.  
An uncommitted comparator provides many application options.  
Status indication and logic shaping/shifting are typical examples.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2001  
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