Monolithic Peak Detector
with Reset-and-Hold Mode
a
PKD01
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Monolithic Design for Reliability and Low Cost
High Slew Rate: 0.5 V/s
+IN –IN
OUTPUT V+
V–
Low Droop Rate
TA = 25؇C: 0.1 mV/ms
TA = 125؇C: 10 mV/ms
–
Low Zero-Scale Error: 4 mV
Digitally Selected Hold and Reset Modes
Reset to Positive or Negative Voltage Levels
Logic Signals TTL and CMOS Compatible
Uncommitted Comparator On-Chip
Available in Die Form
CMP
+
LOGIC
GND
V–
OUTPUT
BUFFER
DET
GATED
"g
–
C
+
"
D
m
1
OUTPUT
–
A
+
–IN
+IN
AMP
GATED
"g
AMP
"
m
–
–IN
+IN
B
+
PKD01
GENERAL DESCRIPTION
RST
The PKD01 tracks an analog input signal until a maximum
amplitude is reached. The maximum value is then retained as a
peak voltage on a hold capacitor. Being a monolithic circuit, the
PKD01 offers significant performance and package density
advantages over hybrid modules and discrete designs without
sacrificing system versatility. The matching characteristics
attained in a monolithic circuit provide inherent advantages
when charge injection and droop rate error reduction are
primary goals.
RST DET OPERATIONAL MODE
C
H
0
0
1
1
0
1
1
0
PEAK DETECT
PEAK HOLD
RESET
SWITCHES SHOWN FOR:
RST = “0,” DET = “0”
INDETERMINATE
The output buffer amplifier features an FET input stage to
reduce droop rate error during lengthy peak hold periods. A bias
current cancellation circuit minimizes droop error at high ambi-
ent temperatures.
Innovative design techniques maximize the advantages of mono-
lithic technology. Transconductance (gm) amplifiers were chosen
over conventional voltage amplifier circuit building blocks. The
g
m amplifiers simplify internal frequency compensation, minimize
Through the DET control pin, new peaks may either be detected
or ignored. Detected peaks are presented as positive output
levels. Positive or negative peaks may be detected without
additional active circuits, since Amplifier A can operate as an
inverting or noninverting gain stage.
acquisition time and maximize circuit accuracy. Their outputs
are easily switched by low glitch current steering circuits. The
steered outputs are clamped to reduce charge injection errors
upon entering the hold mode or exiting the reset mode. The inher-
ently low zero-scale error is further reduced by active Zener-Zap
trimming to optimize overall accuracy.
An uncommitted comparator provides many application options.
Status indication and logic shaping/shifting are typical examples.
REV. A
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use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
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© Analog Devices, Inc., 2001