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PIC24F08KL301

更新时间： 2024-11-08 10:10:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP 闪存微控制器
页数 文件大小 规格书
260页 3191K
描述
Low-Power, Low-Cost, General Purpose 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

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中文翻译

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PIC24F08KL301 数据手册

 浏览型号PIC24F08KL301的Datasheet PDF文件第2页浏览型号PIC24F08KL301的Datasheet PDF文件第3页浏览型号PIC24F08KL301的Datasheet PDF文件第4页浏览型号PIC24F08KL301的Datasheet PDF文件第5页浏览型号PIC24F08KL301的Datasheet PDF文件第6页浏览型号PIC24F08KL301的Datasheet PDF文件第7页 
PIC24F16KL402 FAMILY  
Low-Power, Low-Cost, General Purpose  
16-Bit Flash Microcontrollers with nanoWatt XLP Technology  
Power Management Modes:  
Peripheral Features:  
• High-Current Sink/Source (18 mA/18 mA) on All  
I/O Pins  
• Configurable Open-Drain Outputs on Digital I/O Pins  
• Up to Three External Interrupt Sources  
• Two 16-Bit Timer/Counters with Selectable Clock  
Sources  
• Run – CPU, Flash, SRAM and Peripherals on  
• Doze – CPU Clock Runs Slower than Peripherals  
• Idle – CPU Off, SRAM and Peripherals on  
• Sleep – CPU, Flash and Peripherals Off and SRAM on  
• Low-Power Consumption:  
- Run mode currents under 350 µA/MHz at 1.8V  
- Idle mode currents under 80 µA/MHz at 1.8V  
- Sleep mode currents as low as 30 nA at 25°C  
- Watchdog Timer as low as 210 nA at 25°C  
• Up to Two 8-Bit Timers/Counters with Programmable  
Prescalers  
• Two Capture/Compare/PWM (CCP) modules:  
- Modules automatically configure and drive I/O  
- 16-bit Capture with max. resolution 40 ns  
- 16-bit Compare with max. resolution 83.3 ns  
- 1-bit to 10-bit PWM resolution  
• Up to One Enhanced CCP module:  
- Backward compatible with CCP  
- 1, 2 or 4 PWM outputs  
High-Performance CPU:  
• Modified Harvard Architecture  
• Up to 16 MIPS Operation @ 32 MHz  
• 8 MHz Internal Oscillator:  
- 4x PLL option  
- Multiple divide options  
• 17-Bit x 17-Bit Single-Cycle Hardware  
Fractional/integer Multiplier  
• 32-Bit by 16-Bit Hardware Divider  
• 16 x 16-Bit Working Register Array  
• C Compiler Optimized Instruction Set  
Architecture (ISA):  
- 76 base instructions  
- Flexible addressing modes  
• Linear Program Memory Addressing  
• Linear Data Memory Addressing  
• Two Address Generation Units (AGU) for Separate  
Read and Write Addressing of Data Memory  
- Programmable dead time  
- Auto-shutdown on external event  
• Up to Two Master Synchronous Serial Port modules  
(MSSPs) with Two Modes of Operation:  
- 3-wire SPI (all four modes)  
2
- I C™ Master, Multi-Master and Slave modes and  
7-Bit/10-Bit Addressing  
• Up to Two UART modules:  
- Supports RS-485, RS-232 and LIN/J2602  
- On-chip hardware encoder/decoder for IrDA®  
- Auto-wake-up on Start bit  
- Auto-Baud Detect (ABD)  
- Two-byte transmit and receive FIFO buffers  
Memory  
Peripherals  
Flash  
Program  
(bytes)  
Data  
EEPROM  
(bytes)  
Device  
Pins  
Data  
(bytes)  
PIC24F16KL402  
PIC24F08KL402  
PIC24F16KL401  
PIC24F08KL401  
PIC24F08KL302  
PIC24F08KL301  
PIC24F08KL201  
PIC24F08KL200  
PIC24F04KL101  
PIC24F04KL100  
28  
28  
20  
20  
28  
20  
20  
14  
20  
14  
16K  
8K  
16K  
8K  
8K  
8K  
8K  
8K  
4K  
4K  
1024  
1024  
1024  
1024  
1024  
1024  
512  
512  
512  
512  
512  
256  
256  
—
12  
12  
12  
12  
—
—
12  
7
2
2
2
2
2
2
1
1
1
1
2/2  
2/2  
2/2  
2/2  
2/2  
2/2  
1/2  
1/2  
1/2  
1/2  
2/1  
2/1  
2/1  
2/1  
2/1  
2/1  
2/0  
2/0  
2/0  
2/0  
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
512  
—
512  
—
—
—
512  
—
2011 Microchip Technology Inc.  
DS31037B-page 1  
1234567...260

中文翻译

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