Datasheet > PI6LC48P0301AZHIE

PI6LC48P0301AZHIE

更新时间： 2024-12-01 01:12:35

品牌	Logo	应用领域
百利通 - PERICOM		时钟外围集成电路晶体
页数	文件大小	规格书
12页	1040K
描述
3-Output LVPECL Networking Clock Generator

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PI6LC48P0301AZHIE 数据手册

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PI6LC48P0301A

3-Output LVPECL Networking Clock Generator

Features

Description

ꢀÎree diﬀerential LVPECL output pairs

e PI6LC48P0301A is a 3-output LVPECL synthesizer opti-

mized to generate Ethernet reference clock frequencies and is

a member of Pericom’s HiFlex^TMfamily of high performance

clock solutions. Using a 25MHz or other fundamental frequency

crystal, the most popular Ethernet frequencies can be generated

based on the settings of 4 frequency select pins.

ꢀÎSelectable crystal oscillator interface or LVCMOS/LVTTL

single-ended clock input

ꢀÎSupports the following output frequencies: 125MHz,

156.25MHz, 312.5MHz, 625MHz

ꢀÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal

e PI6LC48P0301A uses Pericom’s proprietary low phase noise

PLL technology to achieve ultra low phase jitter, so it is ideal for

Ethernet interface in all kind of systems.

(12kHz – 20MHz): 0.26ps (typical)

ꢀÎRMS phase jitter @ 156.25MHz, using a 25MHz crystal

(12kHz – 20MHz): 0.4ps (max)

ꢀÎFull 3.3V or 2.5V supply modes

ꢀÎCommercial and industrial ambient operating temperature

ꢀÎAvailable in lead-free package: 28-TQFN

Applications

ꢀÎNetworking systems

Block Diagram

NA_SEL[0:1]

OEA

CLKA

CLKA#

XTAL_IN

OSC

OEB

PFD

VCO

XTAL_OUT

CLKB0

CLKB0#

Ref_IN

CLKB1

CLKB1#

IN_SEL#

PLL_ByPass#

NB_SEL[0:1]

FBN

M_reset

www.pericom.com

PI6LC48P0301A

Rev. A

06/03/2014

14-0083

12 3 4 5 6 7...12

中文翻译

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