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PI6C557-05BLE PDF预览

PI6C557-05BLE

更新时间: 2024-11-21 21:01:47
品牌 Logo 应用领域
美台 - DIODES 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 1009K
描述
Processor Specific Clock Generator, 200MHz, CMOS, PDSO20, TSSOP-20

PI6C557-05BLE 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP, TSSOP20,.25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:24 weeks风险等级:1.31
JESD-30 代码:R-PDSO-G20长度:6.5 mm
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大压摆率:120 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

PI6C557-05BLE 数据手册

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PI6C557-05B  
®
PCIe 3.0 Clock Generator with 4 HCSL Outputs  
Description  
Features  
•ꢀ PCIe®ꢀ3.0ꢀcomplaint  
TheꢀPI6C557-05Bꢀisꢀaꢀspreadꢀspectrumꢀclockꢀgeneratorꢀcompliantꢀ  
toPCIExpress®3.0ꢀandꢀEthernetꢀrequirements.Thedeviceisusedꢀ  
forPCorembeddedsystemstosubstantiallyreduceElectromagneticꢀ  
Interferenceꢀ(EMI).ꢀ  
ꢀ →PCIeꢀ3.0ꢀPhaseꢀjitter:ꢀ0.48psꢀRMSꢀ(HighꢀFreq.ꢀTyp.)  
•ꢀ LVDSꢀcompatibleꢀoutputs  
•ꢀ Supplyꢀvoltageꢀofꢀ3.3Vꢀ±5%  
Theꢀ PI6C557-05Bꢀ providesꢀ fourꢀ differentialꢀ (HCSL)ꢀ orꢀ LVDSꢀ  
spreadspectrumoutputs.ꢀTheꢀPI6C557-05Bꢀisꢀconfiguredꢀtoꢀselectꢀ  
spreadandclockselection.UsingPericom'spatentedPhase-Lockedꢀ  
Loopꢀ(PLL)ꢀtechniques,ꢀtheꢀdeviceꢀtakesꢀaꢀ25MHzꢀcrystalꢀinputꢀ  
andꢀproducesꢀfourꢀpairsꢀofꢀdifferentialꢀoutputsꢀ(HCSL)ꢀatꢀ100MHzꢀ  
andꢀ200MHzꢀclockꢀfrequencies.ꢀItꢀalsoꢀprovidesꢀspreadꢀselectionꢀ  
ofꢀ-0.5%,ꢀ-1.0%,ꢀ-1.5%,ꢀandꢀnoꢀspread.  
•ꢀ 25MHzꢀcrystalꢀorꢀclockꢀinputꢀfrequency  
•ꢀ HCSLꢀoutputs,ꢀ0.7VꢀCurrentꢀmodeꢀdifferentialꢀpair  
•ꢀ Jitterꢀ40psꢀcycle-to-cycleꢀ(typ)  
•ꢀ Spreadꢀofꢀ-0.5%,ꢀ-1.0%,ꢀ-1.5%,ꢀandꢀnoꢀspread  
•ꢀ Industrialꢀtemperatureꢀrange  
•ꢀ SpreadꢀBypassꢀoptionꢀavailable  
•ꢀ Spreadꢀandꢀfrequencyꢀselectionꢀviaꢀexternalꢀpins  
•ꢀ Packaging:ꢀ(Pb-freeꢀandꢀGreen)  
ꢀ →20-pin,ꢀ173-milꢀwideꢀTSSOPꢀ  
Pin Configuration  
Block Diagram  
VDD  
PD  
OE  
1
2
VDDXD  
S0  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
CLK0  
2
CLK0  
Spread  
Spectrum/  
Output  
3
S[2:0]  
SS Circuitry  
PLL  
3
S1  
CLK1  
clock  
4
S2  
CLK0  
CLK0  
CLK1  
CLK1  
CLK2  
CLK1  
selection  
5
X1  
GNDODA  
VDDODA  
CLK2  
6
X2  
X1/CLK  
X2  
25 MHz  
crystal  
Crystal  
Driver  
CLK2  
CLK3  
7
PD  
or clock  
CLK3  
8
OE  
CLK2  
2
Pulling  
R
r(IREF)  
Capacitors  
9
GNDXD  
IREF  
CLK3  
GND  
10  
CLK3  
All trademarks are property of their respective owners.  
www.diodes.com  
3/21/17  
17-0052  
1

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