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PI6C2405A-1HWIEX PDF预览

PI6C2405A-1HWIEX

更新时间: 2024-11-26 14:35:15
品牌 Logo 应用领域
美台 - DIODES 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 862K
描述
Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, LEAD FREE, SOIC-8

PI6C2405A-1HWIEX 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP, SOP8,.25Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.49系列:6C
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
逻辑集成电路类型:CLOCK DRIVER最大I(ol):0.012 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:5最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
传播延迟(tpd):0.3 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.75 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
最小 fmax:133 MHzBase Number Matches:1

PI6C2405A-1HWIEX 数据手册

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PI6C2405A  
Zero-Delay Clock Buffer  
Features  
Description  
ꢀ Maximumꢀratedꢀfrequency:ꢀ133ꢀMHz  
ꢀ Lowꢀcycle-to-cycleꢀjitter  
ꢀ Inputꢀtoꢀoutputꢀdelay,ꢀlessꢀthanꢀ300ps  
TheꢀPI6C2405AꢀisꢀaꢀPLLꢀbased,ꢀzero-delayꢀbuffer,ꢀwithꢀtheꢀabilityꢀ  
toꢀdistributeꢀfiveꢀoutputsꢀofꢀupꢀtoꢀ133MHzꢀatꢀ3.3V.ꢀAllꢀtheꢀoutputsꢀ  
areꢀdistributedꢀfromꢀaꢀsingleꢀclockꢀinputꢀCLKINꢀandꢀoutputꢀOUT0ꢀ  
performsꢀzeroꢀdelayꢀbyꢀconnectingꢀaꢀfeedbackꢀtoꢀPLL.  
ꢀ Internalꢀfeedbackꢀallowsꢀoutputsꢀtoꢀbeꢀsynchronizedꢀ  
AninternalfeedbackonOUT0isusedtosynchronizetheout-  
putsꢀtoꢀtheꢀinput;ꢀtheꢀrelationshipꢀbetweenꢀloadingꢀꢀofꢀthisꢀsignalꢀ  
andꢀ theꢀ outputsꢀ determinesꢀ theꢀ input-outputꢀ delay.ꢀ PI6C2405Aꢀ  
isꢀ ableꢀ toꢀ trackꢀ spreadꢀ spectrumꢀ clockingꢀ forꢀ EMIꢀ reduction.ꢀ  
PI6C2405Aischaracterizedforbothcommercialandindustrialꢀ  
operation.  
toꢀtheꢀclockꢀinput  
ꢀ 5Vꢀtolerantꢀinput*  
ꢀ Spreadꢀspectrumꢀclockꢀready  
ꢀ Operatesꢀatꢀ3.3VꢀV  
ꢀ Packagingꢀ(Pb-freeꢀ&ꢀGreenꢀavailable):ꢀ  
DD  
-8-pin,ꢀ150-milꢀSOICꢀ(W)ꢀ  
PI6C2405A-1Hꢀisꢀaꢀhigh-driveꢀversionꢀofꢀPI6C2405A-1  
ꢀ -8-pin,ꢀ173-milꢀTSSOPꢀ(L)  
* CLKIN must reference the same voltage thresholds for the PLL to  
deliver zero delay skewing  
Block Diagram  
Pin Configuration  
OUT0  
OUT1  
1
2
3
4
8
7
6
5
CLKIN  
OUT  
OUT  
0
PLL  
CLKIN  
OUT  
OUT  
2
4
1
V
DD  
OUT2  
OUT3  
GND  
OUT  
3
PI6C2405A(–1, –1H)  
OUT4  
Pin Description  
Pin  
Signal  
Description  
1
CLKIN  
OUT[1-4]  
GND  
Inputꢀclockꢀreferenceꢀfrequencyꢀ(weakꢀpull-down)  
2,ꢀ3,ꢀ5,ꢀ7  
ClockꢀOutputs  
4
6
8
Ground  
V
3.3VꢀSupply  
DD  
OUT0  
Clockoutput,ꢀinternalꢀPLLꢀfeedbackꢀ(weakꢀpull-down)  
PS8592I  
04/29/10  
1
11-0001  

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