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PI6C2405A-1LX PDF预览

PI6C2405A-1LX

更新时间: 2024-11-26 13:12:19
品牌 Logo 应用领域
百利通 - PERICOM 时钟
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7页 442K
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PI6C2405A-1LX 数据手册

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PI6C2405A  
Zero-Delay Clock Buffer  
Features  
Description  
Maximum rated frequency: 133 MHz  
Low cycle-to-cycle jitter  
Input to output delay, less than 300ps  
The PI6C2405Ais a PLL based, zero-delay buffer, with the ability  
to distribute five outputs of up to 133MHz at 3.3V. All the outputs  
are distributed from a single clock input CLKIN and output OUT0  
performs zero delay by connecting a feedback to PLL.  
Internal feedback allows outputs to be synchronized  
An internal feedback on OUT0 is used to synchronize the out-  
puts to the input; the relationship between loading of this signal  
and the outputs determines the input-output delay. PI6C2405A  
is able to track spread spectrum clocking for EMI reduction.  
PI6C2405A is characterized for both commercial and industrial  
operation.  
to the clock input  
5V tolerant input*  
Spread spectrum clock ready  
Operates at 3.3V V  
Packaging (Pb-free & Green available):  
-8-pin, 150-mil SOIC (W)  
DD  
PI6C2405A-1H is a high-drive version of PI6C2405A-1  
-8-pin, 173-mil TSSOP (L)  
* CLKIN must reference the same voltage thresholds for the PLL to  
deliver zero delay skewing  
Block Diagram  
Pin Configuration  
OUT  
1
0
8
7
6
5
CLKIN  
OUT  
OUT  
0
PLL  
CLKIN  
2
3
4
OUT  
OUT  
2
4
OUT  
OUT  
OUT  
OUT  
1
2
3
4
1
V
DD  
GND  
OUT  
3
PI6C2405A(–1, –1H)  
Pin Description  
Pin  
Signal  
Description  
1
CLKIN  
OUT[1-4]  
GND  
Input clock reference frequency (weak pull-down)  
2, 3, 5, 7  
Clock Outputs  
4
6
8
Ground  
V
3.3V Supply  
DD  
OUT0  
Clockoutput, internal PLL feedback (weak pull-down)  
PS8592D  
09/22/04  
1

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