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PI49FCT3803 PDF预览

PI49FCT3803

更新时间: 2024-10-27 06:03:11
品牌 Logo 应用领域
百利通 - PERICOM 时钟
页数 文件大小 规格书
6页 418K
描述
1:5/1:7 Clock Buffer for Networking Applications

PI49FCT3803 数据手册

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PI49FCT3802/PI49FCT3803  
1:5/1:7 Clock Buffer  
for Networking Applications  
Features  
Description  
• High Frequency >156 MHz  
The PI49FCT380x is a 3.3V compatible, high-speed, low-noise  
non-inverting clock buffer. The key goal in designing the  
PI6C380x is to target networking applications that require low-  
skew, low-jitter, and high-frequency clock distribution. Providing  
output-to-output skew as low as 250ps, the PI49FCT380x is an  
idealclockdistributiondeviceforsynchronoussystems. Designing  
synchronousnetworkingsystemsrequiresatightlevelofskewfrom  
a large number of outputs.  
• High-speed, low-noise, non-inverting buffer  
- PI49FCT3802 is 1:5 buffer  
- PI49FCT3803 is 1:7 buffer  
• Low-skew (<250ps) between any two output clocks  
• Low duty cycle distortion <250ps  
• Low propagation delay <2.5ns  
• 5V Tolerant input  
Pin Description  
• Multiple V , GND pins for noise reduction  
DD  
Pin Name  
Description  
• 3.3V supply voltage  
3802  
3803  
• Packaging (Pb-free & Green available):  
- 16-pin TSSOP (L)  
- 16-pin QSOP (Q)  
BUF_IN  
CLK[0:4]  
GND  
BUF_IN  
CLK[0:4]  
GND  
Input  
Outputs  
GND  
V
V
Power  
DD  
DD  
Pin Configuration (PI49FCT3802)  
Block Diagram (PI49FCT3802)  
CLK0  
BUF_IN  
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
DD  
GND  
CLK4  
CLK3  
GND  
CLK2  
CLK1  
CLK2  
CLK3  
CLK4  
CLK0  
BUF_IN  
16-Pin  
L, Q  
V
DD  
CLK1  
GND  
V
DD  
NC  
NC  
V
GND  
DD  
Pin Configuration (PI49FCT3803)  
Block Diagram (PI49FCT3803)  
CLK0  
CLK1  
CLK2  
CLK3  
BUF_IN  
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
DD  
GND  
CLK6  
CLK5  
GND  
CLK4  
CLK0  
BUF_IN  
16-Pin  
L, Q  
V
DD  
CLK1  
GND  
V
DD  
CLK2  
CLK3  
GND  
V
DD  
CLK6  
PS8559A  
09/14/04  
1

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