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PI2EQXDP101-A PDF预览

PI2EQXDP101-A

更新时间: 2024-11-06 01:23:03
品牌 Logo 应用领域
百利通 - PERICOM /
页数 文件大小 规格书
11页 828K
描述
1 to 1 DisplayPort ReDriver

PI2EQXDP101-A 数据手册

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PI2EQXDP101-A  
1 to 1 DisplayPort™ ReDriver™  
Features  
Description  
•ꢀ DisplayPort™ꢀ1.1aꢀoperationꢀatꢀreducedꢀbitꢀrateꢀ(1.62Gbps)ꢀ  
andꢀhighꢀbitꢀrateꢀ(2.7Gbps)  
ThePI2EQXDP101-AisaoneInputandoneOutputDisplayPort™ꢀ  
ReDriver™ꢀthatꢀsupportꢀaꢀmaximumꢀdataꢀrateꢀofꢀ2.7ꢀGbpsꢀthroughꢀ  
eachꢀchannel,ꢀwhichꢀresultsꢀinꢀaꢀtotalꢀofꢀ10.8Gbpsꢀthrough-put.ꢀꢀ  
•ꢀ Jitterꢀeliminationꢀcircuitsꢀautomaticallyꢀadjustꢀlinkꢀviaꢀtrainingꢀ  
path  
Outputꢀ Levelꢀ Swingꢀ andꢀ Outputꢀ Pre-emphasisꢀ andꢀ numberꢀ ofꢀ  
activeꢀ lanesꢀ areꢀ controlledꢀ byꢀ decodingꢀ theꢀ AUXꢀ commandꢀ  
duringꢀ linkꢀ initialization.Also,ꢀ utilizingꢀ theꢀ HPDꢀ signalsꢀ fromꢀ  
eachDisplayPortport,thePI2EQXDP101-Acanautomaticallyꢀ  
enterꢀpowerꢀdownꢀstate.ꢀꢀOr,ꢀifꢀtheꢀgraphicsꢀdriverꢀisꢀoffꢀandꢀhasꢀ  
noꢀoutputꢀsignal,ꢀPericom’sꢀPI2EQXDP101-Aꢀcanꢀautomaticallyꢀ  
enterꢀlowꢀpowerꢀmode,ꢀevenꢀifꢀanꢀactiveꢀmonitorꢀisꢀattached.  
àꢀ Pre-Emphasis,ꢀandꢀoutputꢀswing  
•ꢀ Canꢀsupportꢀallꢀ4ꢀlevelsꢀofꢀoutputꢀswingꢀandꢀ4ꢀlevelsꢀoutputꢀ  
pre-emphasis,ꢀasꢀspecifiedꢀinꢀtheꢀDisplayPortꢀ1.1aꢀspec.  
•ꢀ AUXꢀinterceptionꢀcircuitꢀonlyꢀlistensꢀtoꢀtheꢀlinkꢀtraining,ꢀbutꢀ  
doesꢀnotꢀaffectꢀlinkꢀtraining  
•ꢀ LowꢀinsertionꢀlossꢀacrossꢀtheꢀAUXꢀsignalꢀpathꢀ(0.35dBꢀ  
@1Mbps)  
•ꢀ OutputꢀcanꢀsupportꢀdualꢀmodeꢀDPꢀbyꢀprovidingꢀDDCꢀsignalsꢀ  
acrossꢀtheꢀAUX_sinkꢀpins  
àꢀ UsingꢀCableꢀDetectꢀpinꢀfromꢀDPꢀconnectorꢀ(pinꢀ13),ꢀ  
theꢀswitchꢀcanꢀtoggleꢀbetweenꢀDPꢀandꢀTMDSꢀmode.  
•ꢀ AutomaticꢀpowerꢀdownꢀstateꢀwhenꢀHPDꢀsignalꢀisꢀLOW  
•ꢀ Entersꢀlowꢀpowerꢀmodeꢀwhenꢀnoꢀdataꢀsignalꢀisꢀpresent  
•ꢀ Dualꢀpowerꢀsupplyꢀ(1.5Vꢀandꢀ3.3V)  
•ꢀ 2KVꢀHBMꢀESDꢀprotection  
•ꢀ 50ꢀohmꢀoutputꢀterminationꢀcanꢀbeꢀturnedꢀoffꢀwhenꢀportꢀisꢀoff  
àꢀ Portꢀisꢀturnedꢀoffꢀautomaticallyꢀwhenꢀnotꢀneeded  
•ꢀ Packageꢀ(Pb-Freeꢀ&ꢀGreenꢀavailable)  
àꢀ 36-pinꢀTQFNꢀ(ZF)  
Block Diagram  
Pin Diagram (Top-side View)  
IN [3:0]±  
Equalizer  
Pre-emphasis  
OUT [3:0]±  
33  
36 35 34  
32 31 30 29  
OUT0+  
OUT0-  
IN0+  
IN0-  
IN1+  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
HPD SRC  
CAD SRC  
Logics  
HPD_Sink  
CAD_Sink  
Bias  
3
OUT1+  
4
OUT1-  
GND  
IN1-  
DDC_SCL/AUX+  
DDC_SDA/AUX-  
AUX_SRC+  
AUX_SRC-  
AUX  
Pass  
through  
VDD15  
5
IN2+  
IN2-  
6
OUT2+  
OUT2-  
VDD15  
OUT3+  
OUT3-  
AUX CH  
interpreter  
register  
7
GND  
8
SCL  
SDA  
DDC  
Pass  
through  
9
IN3+  
IN3-  
10  
14  
11 12 13  
15 16 17 18  
P-0.3  
07/09/10  
10-0194  
1

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