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PEEL22LV10AZT-25L PDF预览

PEEL22LV10AZT-25L

更新时间: 2024-11-16 20:18:31
品牌 Logo 应用领域
ICT 时钟光电二极管可编程逻辑
页数 文件大小 规格书
10页 683K
描述
EE PLD, 25ns, CMOS, PDSO24, 0.170 INCH, LEAD FREE, TSSOP-24

PEEL22LV10AZT-25L 技术参数

生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.3Is Samacsys:N
其他特性:10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK最大时钟频率:25 MHz
JESD-30 代码:R-PDSO-G24长度:7.8 mm
专用输入次数:11I/O 线路数量:10
端子数量:24最高工作温度:70 °C
最低工作温度:组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH可编程逻辑类型:EE PLD
传播延迟:25 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压:3.6 V
最小供电电压:2.7 V标称供电电压:3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

PEEL22LV10AZT-25L 数据手册

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PEEL™ 22LV10AZ-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Low Voltage, Ultra Low Power Operation  
Architectural Flexibility  
- Vcc = 2.7 to 3.6 V  
-
Enhanced architecture fits in more logic  
- Icc = 5 µA (typical) at standby  
3- 133 product terms x 44 input AND array  
- Icc = 1.5 mA (typical) at 1 MHz  
- Meets JEDEC LV Interface Spec (JESD8-A)  
- 5 Volt tolerant inputs and I/O’s  
-
-
-
-
-
-
-
-
12 inputs and 10 I/O pins  
12 possible macrocell configurations  
Asynchronous clear, synchronous preset  
Independent output enables  
CMOS Electrically Erasable Technology  
- Superior factory testing  
Programmable clock; pin 1 or p-term  
Programmable clock polarity  
24 Pin DIP/SOIC/TSSOP and 28 Pin PLCC  
Schmitt triggers on clock and data inputs  
-
Reprogrammable in plastic package  
-
Reduces retrofit and development costs  
Application Versatility  
-
-
-
-
-
Replaces random logic  
Schmitt Trigger Inputs  
Super set of standard PLDs  
-
Eliminates external Schmitt trigger devices  
Pin and JEDEC compatible with 22V10  
Ideal for battery powered systems  
Replaces expensive oscillators  
- Ideal for encoder designs  
General Description  
The PEEL™22LV10AZ is a Programmable Electrically Erasable  
Logic (PEEL™) SPLD (Simple Programmable Logic Device) that  
operates over the supply voltage range of 2.7V-3.6V and fea- tures  
ultra-low, automatic “zero” power-down operation. The  
PEEL™22LV10AZ is logically and functionally similar to Ana-  
chip’s 5V PEEL™22CV10A+ and PEEL™22CV10AZ. The  
“zero power” (50 µA max. Icc) power-down mode makes the  
PEEL™22LV10AZ ideal for a broad range of battery-powered  
portable equipment applications, from hand-held meters to PCM-  
CIA modems. EE-reprogrammability provides both the conve-  
nience of fast reprogramming for product development and quick  
product personalization in manufacturing, including Engineering  
Change Orders.  
The differences between the PEEL™22LV10AZ and  
PEEL™22CV10A include the addition of programmable clock  
polarity, p-term clock, and Schmitt trigger input buffers on all  
inputs, including the clock. Schmitt trigger inputs allow direct  
input of slow signals such as biomedical and sine waves or  
clocks. Like the PEEL™22CV10, the PEEL™22LV10AZ is a pin  
and JEDEC compatible, logical superset of the industry stan- dard  
PAL22V10 SPLD (Figure 26). The PEEL™22LV10AZ pro- vides  
additional architectural features that allow more logic to be  
incorporated into the design. The PEEL™22LV10AZ architec-  
ture allows it to replace over twenty standard 24-pin DIP, SOIC,  
TSSOP and PLCC packages.  
Figure 26 Block Diagram  
Figure 26 Pin Configuration  
I/CLK  
1
24  
VCC  
I
I
2
23  
22  
I/O  
I/O  
3
I
I
4
5
21  
20  
I/O  
I/O  
I/O  
I/O  
19  
I
I
6
7
18  
17  
16  
15  
I
I
I
8
I/O  
I/O  
I/O  
9
10  
I
11  
12  
14  
13  
I/O  
I
GND  
TSSOP  
DIP  
PLCC  
SOIC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent  
accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  

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