Commercial/Industrial
PEEL™ 22LV10AZ-25 / I-35
CMOS Programmable Electrically Erasable Logic Device
Features
•
Low Voltage, Ultra Low Power Operation
•
Architectural Flexibility
- Vcc = 2.7 to 3.6 V
- Enhanced architecture fits in more logic
- 133 product terms x 44 input AND array
- 12 inputs and 10 I/O pins
- 12 possible macrocell configurations
- Asynchronous clear, synchronous preset
- Independent output enables
- Programmable clock; pin 1 or p-term
- Programmable clock polarity
- 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC
- Schmitt triggers on clock and data inputs
- Icc = 5 µA (typical) at standby
- Icc = 1.5 mA (typical) at 1 MHz
- Meets JEDEC LV Interface Spec (JESD8-B)
- 5 Volt tolerant inputs and I/O’s
•
•
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super set of standard PLDs
- Pin and JEDEC compatible with 22V10
- Ideal for battery powered systems
- Replaces expensive oscillators
•
Schmitt Trigger Inputs
- Eliminates external Schmitt trigger devices
- Ideal for encoder designs
General Description
The PEEL22LV10AZ is a Programmable Electrically The differences between the PEEL22LV10AZ and
Erasable Logic (PEEL) SPLD (Simple Programmable PEEL22CV10A include the addition of programmable
Logic Device) that operates over the supply voltage clock polarity, p-term clock, and Schmitt trigger input
range of 2.7V-3.6V and features ultra-low, automatic buffers on all inputs, including the clock. Schmitt trigger
"zero" power-down operation. The PEEL22LV10AZ is inputs allow direct input of slow signals such as
logically and functionally similar to ICT's 5V biomedical and sine waves or clocks. Like the
PEEL22CV10A and PEEL22CV10AZ. The "zero power" PEEL22CV10A, the PEEL22LV10AZ is a pin and
JEDEC compatible, logical superset of the industry
standard PAL22V10 SPLD Figure 1. The
PEEL22LV10AZ provides additional architectural
features that allow more logic to be incorporated into
the design. The PEEL22LV10AZ architecture allows it
to replace over twenty standard 24-pin DIP, SOIC,
(25 µA max. ICC) power-down mode makes the
PEEL22LV10AZ ideal for a broad range of battery-
powered portable equipment applications, from hand-
held
meters
to
PCMCIA
modems.
EE-
reprogrammability provides both the convenience of
product fast reprogramming for product development
and quick personalization in manufacturing, including
Engineering Change Orders.
TSSOP
and
PLCC
packages.
Figure 1 - Pin Configuration
Figure 2 - Block Diagram
I/CLK
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/CLK
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
CLK MUX (Optional)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SP
AC
I/CLK
I
I
I
I
I
I
I
I
I
I
I
TM
PEEL
OE
"AND"
ARRAY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10
11
12 13
I
I
10
11
12
I
I
MACRO
CELL
133 Terms
X
GND
GND
44 Inputs
TSSOP
DIP
3
2
1
28 27 26
4
I/O
I/O
I/O
NC
I/O
I/O
I/O
I
I
I
5
6
7
8
9
25
1
2
3
4
5
6
7
8
24
23
I/CLK
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
24
23
22
21
20
19
I
22
21
20
19
18
17
16
15
14
13
I
NC
I
SP = SYNCHRONOUS PRESET
I
I
I
I
I
AC = ASYNCHRONOUS CLEAR
OE = OUTPUT ENABLE
10
11
I
I
12 1314 15 1617 18
9
I
10
11
12
I
I
GND
SOIC
PLCC
1
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