Datasheet > PEEL22CV10A

PEEL22CV10A

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
易亨 - ANACHIP		/
页数	文件大小	规格书
10页	339K
描述
CMOS Programmable Electrically Erasable Logic Device

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PEEL22CV10A 数据手册

PEEL™ 22CV10A-7/-10/-15/-25

CMOS Programmable Electrically Erasable Logic Device

Features

High Speed/Low Power

Architectural Flexibility

- Speeds ranging from 7ns to 25ns

- 132 product term X 44 input AND array

- Up to 22 inputs and 10 outputs

- Power as low as 30mA at 25MHz

- Up to 12 configurations per macrocell

- Synchronous preset, asynchronous clear

- Independent output enables

Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC

Application Versatility

Development/Programmer Support

- Third party software and programmers

- Anachip PLACE Development Software

- Replaces random logic

- Pin and JEDEC compatible with 22V10

- Enhanced Architecture fits more logic

than ordinary PLDs

General Description

The PEEL™22CV10A is a Programmable Electrically Eras-

able Logic (PEEL™) device providing an attractive alterna-

tive to ordinary PLDs. The PEEL™22CV10A offers the

performance, flexibility, ease of design and production

practicality needed by logic designers today. The

PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP

and 28-pin PLCC packages (see Figure 1), with speeds

ranging from 7ns to 25ns and with power consumption as low

as 30mA. EE-reprogrammability provides the conve- nience

of instant reprogramming for development and a reusable

also improves factory testability, thus ensuring the highest

quality possible. The PEEL™22CV10A is JEDEC file com-

patible with standard 22V10 PLDs. Eight additional configu-

rations per macrocell (a total of 12) are also available by

using the “+” software/programming option (i.e., 22CV10A+

& 22CV10A++). The additional macrocell configurations

allow more logic to be put into every design. Programming

and development support for the PEEL™22CV10A are pro-

vided by popular third-party programmers and develop-

ment software. Anachip also offers free PLACE

development software.

production

inventory,

minimizing

the

impact

programming changes or errors. EE-reprogrammability

Figure 1. Pin Configuration

Figure 2. Block Diagram

I/CLK

VCC

I/O

GND

TSSOP

DIP

SOIC

PLCC

*Optional extra ground pin for

-7/I-7 speed grade.

This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under

any patent accompany the sale of the product.

Rev. 1.0 Dec 16, 2004

1/10

12 3 4 5 6 7...10

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