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PEEL16CV8T-25L PDF预览

PEEL16CV8T-25L

更新时间: 2024-11-21 20:12:03
品牌 Logo 应用领域
美台 - DIODES 时钟光电二极管可编程逻辑
页数 文件大小 规格书
11页 397K
描述
EE PLD, 25ns, PAL-Type, CMOS, PDSO20, LEAD FREE, TSSOP-20

PEEL16CV8T-25L 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.3
架构:PAL-TYPE最大时钟频率:28.5 MHz
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:6.5 mm湿度敏感等级:3
专用输入次数:9I/O 线路数量:8
输入次数:18输出次数:8
产品条款数:64端子数量:20
最高工作温度:70 °C最低工作温度:
组织:9 DEDICATED INPUTS, 8 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:5 V
可编程逻辑类型:EE PLD传播延迟:25 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Programmable Logic Devices最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

PEEL16CV8T-25L 数据手册

 浏览型号PEEL16CV8T-25L的Datasheet PDF文件第2页浏览型号PEEL16CV8T-25L的Datasheet PDF文件第3页浏览型号PEEL16CV8T-25L的Datasheet PDF文件第4页浏览型号PEEL16CV8T-25L的Datasheet PDF文件第5页浏览型号PEEL16CV8T-25L的Datasheet PDF文件第6页浏览型号PEEL16CV8T-25L的Datasheet PDF文件第7页 
Notrecommendedfor Newdesigns-  
contactfactoryforavailability
PEEL™ 16CV8 -25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Compatible with Popular 16V8 Devices  
- 16V8 socket and function compatible  
Multiple Speed, Power Options  
- Speeds range 25ns  
- Programs with standard 16V8 JEDEC file  
- 20-pin DIP, SOIC, TSSOP, and PLCC  
- Power as low as 37mA @ 25mHZ  
Development / Programmer Support  
- Third party software and programmers  
CMOS Electrically Erasable Technology  
- Superior factory testing  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
- Anachip WinPLACE Development Software  
- Automatic programmer translation and JEDEC file translation  
software available for the most popular PAL devices  
Application Versatility  
- Replaces random logic  
- Super sets standard 20-pin PLDs (PALs)  
General Description  
The PEELTM 16CV8 is a Programmable Electrically Erasable Logic  
The PEELTM 16CV8 architecture allows it to replace over standard 20-  
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. Anachip’s PEELTM  
16CV8 can be programmed with existing 16CV8 JEDEC file. Some pro-  
grammers also allow the PEELTM 16CV8 to be programmed directly  
from PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional develop-  
ment and programming support for the PEELTM16CV8 is provided by  
popular third-party programmers and development software. Anachip  
also offers free WinPLACE development software.  
(PEEL) device providing an attractive alternative to ordinary PLDs. The  
PEELTM 16CV8 offers the performance, flexibility, ease of design and  
production practicality needed by logic designers today.  
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP  
packages (see Figure 1) with 25ns speed and power consumption as low  
as 37mA. EE-Reprogrammability provides the convenience of instant  
reprogramming for development and reusable production inven- tory  
minimizing the impact of programming changes or errors. EE-  
Reprogrammability also improves factory testability, thus assuring the  
highest quality possible.  
Figure 1 - Pin Configuration  
Figure 2 - Block Diagram  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under  
any patent accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/11  

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