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PE3745BEF-120.0M PDF预览

PE3745BEF-120.0M

更新时间: 2024-10-28 19:01:03
品牌 Logo 应用领域
PLETRONICS /
页数 文件大小 规格书
4页 72K
描述
Oscillator

PE3745BEF-120.0M 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.57Base Number Matches:1

PE3745BEF-120.0M 数据手册

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Pl tronics, Inc.  
.
19013 36th Ave. W, Suite H Lynnwood, WA 98036 USA  
Manufacturer of High Quality Frequency Control Products  
Differential PECL Series  
Differential PECL Output, Some with Enable/ Disable Function  
Available in 9 Different Package/Configurations, See Next Pages  
Standard Specifications  
Overall Frequency Stability  
± 50 PPM, ± 25 PPM, ± 20 PPM over Operating Temperature Range  
Operating Temperature Range 0 to +80°C is standard, but can be extended to - 40 to +85°C  
Storage Temperature Range  
Supply Voltage (Vcc)  
Supply Current (Icc)  
- 55 to +125°C  
3.3 volts ± 5% standard, but 5.0 volts or 2.5 volts also available. See Test Cirucit 5.  
< 250 MHz = 90 mA maximum, 250 MHz and above = 100 mA maximum  
Output High Level  
2.275 V minimum referenced to Ground, Vcc = 3.300V,  
0.975 V minimum referenced to termination voltage,  
- 1.025 V minimum referenced to Vcc  
Output Low Level  
1.680 V maximum referenced to Ground, Vcc = 3.300V,  
0.380 V maximum referenced to termination voltage,  
- 1.620 V maximum referenced to Vcc  
Output Symmetry  
Output Rise & Fall (Tr & Tf)  
Jitter  
E/D Internal Pullup  
V disable  
45/55% referenced to 50% of amplitude  
1.0 nS maximum when Vth is 10% and 90% of waveform  
1 pS RMS maximum measured from 12 kHz to 20 MHz from Fnominal  
50 kohm minimum to Vcc  
0.3 Vcc maximum referenced to Ground  
V enable  
0.7 Vcc minumum referenced to Ground  
PE7745D only Output Enable / Disable  
High Level Input Current  
Low Level Input Current  
Output Enable Time  
-20 uA maximum at Enable / Disable Pin = 0.7 Vcc  
-200 uA maximum at Enable / Disable Pin = 0 V  
200 nS maximum at output enable or 1 mS maximum at output enabled and stable  
200 nS maximum at output disable  
Output Disable Time  
Vcc Supply Current disabled < 1 mA. Both outputs are high impedance when disabled.  
All other models Output Enable/Disable (E/D)  
Output Enable Time  
Output Disable Time  
When Disabled  
100 nS maximum  
100 nS maximum  
Q Output = Logic Low, QN Output = Logic High. Both Outputs are active  
Note 1:  
PECL and ECL are identical circuits.  
ECL has the most positive pin as ground and is ideally terminated by 50 ohms to - 2.00 V  
PECL has the most negative pin as ground and is ideally terminated by 50 ohms to the most (positive voltage less 2.00 V)  
Mechanical: See Next Pages  
D Package  
J Package Replacement  
B Package  
M Package  
Mar 2004  
(425) 776 -1880, Fax: (425) 776-2760, ple-sales@pletronics.com, www.pletronics.com  
1
Pl tronics, Inc.  

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