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PDM41028LA12SOATY PDF预览

PDM41028LA12SOATY

更新时间: 2024-10-29 20:21:31
品牌 Logo 应用领域
IXYS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 237K
描述
Standard SRAM, 256KX4, 12ns, CMOS, PDSO28, 0.400 INCH, PLASTIC, SOJ-28

PDM41028LA12SOATY 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOJ
包装说明:0.400 INCH, PLASTIC, SOJ-28针数:28
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.21
最长访问时间:12 nsJESD-30 代码:R-PDSO-J28
长度:18.42 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:4
功能数量:1端子数量:28
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:256KX4
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:3.6 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

PDM41028LA12SOATY 数据手册

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PDM41028  
1 Megabit Static RAM  
256K x 4-Bit  
1
2
Description  
Features  
The PDM41028 is a high-performance CMOS static  
RAM organized as 262,144 x 4 bits. Writing to this  
device is accomplished when the write enable (WE)  
and the chip enable (CE) inputs are both LOW.  
Reading is accomplished when WE remains HIGH  
and CE and OE are both LOW.  
High speed access times  
Com’l: 10, 12 and 15 ns  
Ind’l: 12 and 15 ns  
Low power operation (typical)  
- PDM41028SA  
3
Active: 400 mW  
Standby: 150 mW  
- PDM41028LA  
Active: 350 mW  
Standby: 100 mW  
The PDM41028 operates from a single +5V power  
supply and all the inputs and outputs are fully TTL-  
compatible. The PDM41028 comes in two versions,  
the standard power version PDM41028SA and a low  
power version the PDM41028LA. The two versions  
are functionally the same and only differ in their  
power consumption.  
Single +5V (±10%) power supply  
TTL-compatible inputs and outputs  
Packages  
5
The PDM41028 is available in a 28-pin 300-mil SOJ,  
and a 28-pin 400-mil SOJ for surface mount  
applications.  
Plastic SOJ (300 mil) - TSO  
Plastic SOJ (400 mil) - SO  
6
Functional Block Diagram  
7
A0  
Decoder  
Memory  
8
Addresses  
Matrix  
A17  
• • • • •  
Column I/O  
9
I/O0  
I/O1  
I/O2  
I/O3  
Input  
Data  
Control  
10  
11  
12  
CE  
WE  
OE  
Rev. 2.2 - 4/29/98  
1

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