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PDM34078SA10QA PDF预览

PDM34078SA10QA

更新时间: 2024-02-13 13:06:53
品牌 Logo 应用领域
IXYS 静态存储器
页数 文件大小 规格书
14页 312K
描述
SRAM

PDM34078SA10QA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QFP, QFP100,.7X.9Reach Compliance Code:unknown
风险等级:5.92最长访问时间:10 ns
最大时钟频率 (fCLK):60 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:32端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:32KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified最大待机电流:0.003 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.23 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUADBase Number Matches:1

PDM34078SA10QA 数据手册

 浏览型号PDM34078SA10QA的Datasheet PDF文件第2页浏览型号PDM34078SA10QA的Datasheet PDF文件第3页浏览型号PDM34078SA10QA的Datasheet PDF文件第4页浏览型号PDM34078SA10QA的Datasheet PDF文件第6页浏览型号PDM34078SA10QA的Datasheet PDF文件第7页浏览型号PDM34078SA10QA的Datasheet PDF文件第8页 
PDM34078  
Synchronous Truth Table (See Notes 1 through 3)  
CE CE2 CE2 ADSP ADSC ADV BWx CLK  
Address  
Operation  
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
N/A  
N/A  
Deselected  
1
2
Deselected  
L
X
L
L
N/A  
Deselected  
L
H
H
L
N/A  
Deselected  
L
X
H
H
X
X
X
X
H
X
X
X
X
L
N/A  
Deselected  
L
X
L
External  
External  
Next  
Read Cycle, Begin Burst  
Read Cycle, Begin Burst  
Read Cycle, Continue Burst  
Read Cycle, Continue Burst  
Read Cycle, Suspend Burst  
Read Cycle, Suspend Burst  
Write Cycle, Begin Burst  
Write Cycle, Continue Burst  
Write Cycle, Continue Burst  
Write Cycle, Suspend Burst  
Write Cycle, Suspend Burst  
L
L
H
H
X
H
X
H
H
X
H
H
3
X
H
X
H
L
X
X
X
X
L
H
H
H
H
L
L
Next  
H
H
X
L
Current  
Current  
External  
Next  
4
X
H
X
H
X
X
X
X
H
H
H
H
L
L
L
Next  
5
H
H
L
Current  
Current  
L
NOTES:  
1. X = Don’t Care, H = logic High, L = logic Low, BWx = any one or more byte write enable signals (BW1, BW2, BW3, BW4)  
and BWE are low, or GW is low.  
2. BW1 enables BWx to Byte 1 (DQ1-DQ8). BW2 enables BWx to Byte 2 (DQ9-DQ16).  
BW3 enables BWx to Byte 3 (DQ17-DQ24), BW4 enables BWx to Byte 4 (DQ25-DQ32).  
3. ADV must always be high at the rising edge of the first clock after an ADSP cycle is initiated if a write cycle is desired (to  
ensure use of correct address).  
7
8
9
10  
11  
12  
Rev 1.0 - 5/01/98  
5