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PDM34078SA10QA PDF预览

PDM34078SA10QA

更新时间: 2024-01-31 17:54:22
品牌 Logo 应用领域
IXYS 静态存储器
页数 文件大小 规格书
14页 312K
描述
SRAM

PDM34078SA10QA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QFP, QFP100,.7X.9Reach Compliance Code:unknown
风险等级:5.92最长访问时间:10 ns
最大时钟频率 (fCLK):60 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:32端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:105 °C
最低工作温度:-40 °C组织:32KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified最大待机电流:0.003 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.23 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUADBase Number Matches:1

PDM34078SA10QA 数据手册

 浏览型号PDM34078SA10QA的Datasheet PDF文件第1页浏览型号PDM34078SA10QA的Datasheet PDF文件第2页浏览型号PDM34078SA10QA的Datasheet PDF文件第3页浏览型号PDM34078SA10QA的Datasheet PDF文件第5页浏览型号PDM34078SA10QA的Datasheet PDF文件第6页浏览型号PDM34078SA10QA的Datasheet PDF文件第7页 
PDM34078  
Pinout  
Name  
I/O  
Description  
Name  
I/O  
Description  
A14-A2  
A1, A0  
DQ1-DQ32  
NC  
I
Address Inputs A14-A2  
Address Inputs A1 & A0  
Read/Write Data  
CE, CE2, CE2  
BWE  
I
I
Chip Enables  
I
Byte Write Enable  
Byte Write Enables  
Output Enable  
Clock  
I/O  
BW1-BW4  
OE  
I
No Connect  
I
(1)  
MODE  
I
I
I
I
I
I
Burst Sequence Select  
Burst Counter Advance  
Controller Address Status  
Processor Address Status  
Global Write  
CLK  
I
ADV  
ZZ  
I
Sleep Mode  
ADSC  
ADSP  
GW  
V
V
V
V
Power Supply (+3.3V)  
CC  
Output Power for DQ’s (+3.3V ±5%)  
Array Ground  
CCQ  
SS  
(1)  
FT  
Must be tied HIGH for  
proper operation  
Output Ground for DQ’s  
SSQ  
NOTE: 1.MODE and FT are DC operated pins. Do not alter input state while device is operating.  
Burst Sequence Table  
(1)  
Interleaved  
(2)  
Linear  
Mode = V  
Burst Sequence  
Mode = NC or  
SS  
V
CC  
External Address  
1st Burst Address  
2nd Burst Address  
3rd Burst Address  
A14-A2, A1, A0  
A14-A2, A1, A0  
A14-A2, A1, A0  
A14-A2, A1, A0  
A14-A2,0,0  
A14-A2,0,1  
A14-A2,1,0  
A14-A2,1,1  
A14-A2,0,1  
A14-A2,1,0  
A14-A2,1,1  
A14-A2,0,0  
A14-A2,1,0  
A14-A2,1,1  
A14-A2,0,0  
A14-A2,0,1  
A14-A2,1,1  
A14-A2,0,0  
A14-A2,0,1  
A14-A2,1,0  
Note: 1. Interleaved = x86 and Pentium.  
2. Linear = 680x0 and Power PC compatible.  
Partial Truth Table for Writes  
Asynchronous Truth Table  
Operation  
ZZ  
OE I/O Status  
GW BWE BW1 BW2 BW3 BW4  
Function  
Read  
L
L
L
L
H
L
H
X
X
X
Data Out  
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
READ  
Read  
High-Z  
READ  
Write  
High-Z: Write Data In  
High-Z  
WRITE Byte 1  
WRITE All Bytes  
WRITE All Bytes  
Deselected  
Sleep  
L
High-Z  
X
X
X
X
NOTE: 1. L = Low, H = High, X = Don’t Care.  
2. For a write operation following a read operation,  
OE must be high before the input data required  
setup time and held high through the input data  
hold time.  
NOTE: 1. L = Low, H = High, X = Don’t Care.  
2. Using BWE and BW1 through BW4, any one or  
more bytes may be written.  
3. This device contains circuitry that will ensure  
the outputs will be in high-Z during powerup.  
4
Rev 1.0 - 5/01/98