Datasheet > PDM34078S6Q

PDM34078S6Q

更新时间： 2024-11-21 13:50:19

品牌	Logo	应用领域
IXYS		静态存储器
页数	文件大小	规格书
14页	316K
描述
SRAM

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技术参数
数据手册

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PDM34078S6Q 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.84
Is Samacsys：	N	Base Number Matches：	1

PDM34078S6Q 数据手册

PDM34078

3.3V 32K x 32 Fast CMOS

Synchronous Static RAM

with Burst Counter

and Output Register

Description

Features

The PDM34078 is a 1,048,576 bit synchronous

random access memory organized as 32,768 x 32

bits. This device designed with burst mode

capability and interface controls to provide high-

performance in second level cache designs for x86,

Pentium, 680x0, and PowerPC microprocessors.

Addresses, write data and all control signals except

output enable are controlled through positive edge-

triggered registers. Write cycles are self-timed and

are also initiated by the rising edge of the clock.

Controls are provided to allow burst reads and

writes of up to four words in length. A 2-bit burst

address counter controls the two least-signiﬁcant

bits of the address during burst reads and writes.

The burst address counter selectively uses the 2-bit

counting scheme required by the x86 and Pentium

or 680x0 and PowerPC microprocessors as con-

trolled by the mode pin. Individual write strobes

provide byte write for the four 8-bit bytes of data.

An asynchronous output enable simpliﬁes interface

to high-speed buses.

■ Interfaces directly with the x86, Pentium™, 680X0

and PowerPC™ processors

(100, 80, 66, 60, 50 MHz)

■ Single 3.3V power supply

■ Mode selectable for interleaved or linear burst:

Interleaved for x86 and Pentium

Linear for 680x0 and PowerPC

■ High-speed clock cycle times:

10, 12.5, 15, 16.7 and 20 ns

■ High-density 32K x 32 architecture with burst

address counter and output register

■ Fully registered inputs and outputs for pipelined

operation

■ High-output drive: 30 pF at rated T

■ Asynchronous output enable

■ Self-timed write cycle

■ Separate byte write enables and one global write

enable

■ Internal burst read/write address counter

■ Internal registers for address, data, controls

■ Output data register

■ Burst mode selectable

■ Sleep mode

■ Packages:

100-pin QFP - (Q)

100-pin TQFP - (TQ)

i486, Pentium are trademarks of Intel Corp. PowerPC is a trademark of the International Business Machines Corporation.

Rev 1.0 - 5/01/98

12 3 4 5 6 7...14

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