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PDM31024LL85ST PDF预览

PDM31024LL85ST

更新时间: 2024-02-20 18:12:03
品牌 Logo 应用领域
IXYS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 221K
描述
Standard SRAM, 128KX8, 85ns, CMOS, PDSO32

PDM31024LL85ST 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
最长访问时间:85 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP32,.56,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified最大待机电流:0.000006 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.03 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUALBase Number Matches:1

PDM31024LL85ST 数据手册

 浏览型号PDM31024LL85ST的Datasheet PDF文件第2页浏览型号PDM31024LL85ST的Datasheet PDF文件第3页浏览型号PDM31024LL85ST的Datasheet PDF文件第4页浏览型号PDM31024LL85ST的Datasheet PDF文件第5页浏览型号PDM31024LL85ST的Datasheet PDF文件第6页浏览型号PDM31024LL85ST的Datasheet PDF文件第7页 
PRELIMINARY  
PDM31024LL  
128K x 8-Bit Low Power  
3.3 Volt  
Description  
Features  
The PDM31024LL is a very low power CMOS static  
RAM organized as 131,072 x 8 bits. Writing to this  
device is accomplished when the write enable (WE)  
and the chip enable (CE1) inputs are both LOW, and  
CE2 is high. Reading is accomplished when WE and  
CE2 remain HIGH and CE1 and OE are both LOW.  
High-speed access times  
Com’l: 70, 85 and 100ns  
Low power operation (typical)  
- PDM31024LL  
Active: 50 mW  
Standby: 2µW  
The PDM31024LL operates from a single +3.3V  
power supply and all the inputs and outputs are  
fully TTL- compatible. The device supports low data  
retention voltage for battery back-up operation with  
low current.  
Single +3.3V (±0.3V) power supply  
TTL-compatible inputs and outputs  
I/Os are 5V tolerant  
The PDM31024LL is available in a 32-pin plastic  
TSOP (I) and a 32-pin plastic STSOP (I).  
Low data retention voltage: 1.5V  
Packages  
Plastic TSOP (I) - T  
Plastic STSOP (I) - ST  
Functional Block Diagram  
A0  
Decoder  
Memory  
Addresses  
Matrix  
A16  
• • • •  
I/O0  
Input  
Column I/O  
Data  
Control  
I/O7  
CE1  
CE2  
WE  
OE  
Control  
Rev. 0.0 - 4/03/98  
1

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