Philips Semiconductors
Preliminary data
1-port 400 Mbps physical layer interface
PDI1394P25
1.0 FEATURES
• Fully supports provisions of IEEE 1394–1995 Standard for high
• Supports extended bias-handshake time for enhanced
1
performance serial bus and the P1394a–2000 Standard
interoperability with camcorders
• Fully interoperable with Firewire and i.LINK implementations of
• Interface to link-layer controller supports both low-cost bus-holder
2
the IEEE 1394 Standard.
isolation and optional Annex J electrical isolation
• Full P1394a support includes:
– Connection debounce
• Data interface to link-layer controller through 2/4/8 parallel lines at
49.152 MHz
– Arbitrated short reset
• Low-cost 24.576 MHz crystal provides transmit, receive data at
– Multispeed concatenation
– Arbitration acceleration
– Fly-by concatenation
100/200/400 Mbps, and link-layer controller clock at 49.152 MHz
• Does not require external filter capacitors for PLL
• Interoperable with link-layer controllers using 3.3 V and 5 V
– Port disable/suspend/resume
supplies
• Provides one 1394a fully-compliant cable port at
100/200/400 Mbps. Can be used as a one port PHY without the
use of any extra external components
• Interoperable with other Physical Layers (PHYs) using 3.3 V and
5 V supplies
• Node power class information signaling for system power
• Fully compliant with Open HCI requirements
management
• Cable ports monitor line conditions for active connection to remote
• Cable power presence monitoring
node.
• Separate cable bias (TPBIAS) for each port
• Power down features to conserve energy in battery-powered
applications include:
• Register bits give software control of contender bit, power class
– Automatic device power down during suspend
– Device power down terminal
bits, link active bit, and 1394a features
• LQFP package is function and pin compatible with the Texas
Instruments TSB41LV01E and TSB41AB1 (PAP package)
400 Mbps PHYs.
– Link interface disable via LPS
– Inactive ports powered-down
• Logic performs system initialization and arbitration functions
2.0 DESCRIPTION
• Encode and decode functions included for data-strobe bit level
The PDI1394P25 provides the digital and analog transceiver functions
needed to implement a one port node in a cable-based IEEE
1394–1995 and/or 1394a network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to
monitor the line conditions as needed for determining connection
status, for initialization and arbitration, and for packet reception and
transmission. The PDI1394P25 is designed to interface with a Link
Layer Controller (LLC), such as the PDI1394L40 or PDI1394L41.
encoding
• Incoming data resynchronized to local clock
• Single 3.3 volt supply operation
• Minimum V of 2.7 V for end-of-wire power-consuming devices
DD
• While unpowered and connected to the bus, will not drive TPBIAS
on a connected port, even if receiving incoming bias voltage on
that port
3.0 ORDERING INFORMATION
PACKAGE
64-pin plastic LQFP
64-ball plastic LFBGA
TEMPERATURE RANGE
0 to +70°C
ORDER CODE
PDI1394P25BD
PDI1394P25EC
PKG. DWG. #
SOT314-2
0 to +70°C
SOT534-1
1.
2.
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.
Firewire is a trademark of Apple Computer Inc. i.LINK is a trademark of Sony.
2
2001 Sep 06
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