Philips Semiconductors
Preliminary data
1-port 400 Mbps physical layer interface
PDI1394P25
Name
Pin Type
LQFP
Pin
LFBGA
Ball
I/O
Description
Numbers Numbers
D0–D7
CMOS 5 V tol
6, 7, 8,
9, 10, 11,
12, 13
H3, H4,
E4, H5,
F4, G5,
F5, H6
I/O
Data I/Os. These are bi-directional data signals between the
PDI1394P25 and the LLC. Bus holders are built into these terminals.
Unused Dn pins should be pulled to ground through 10 kΩ resistors.
DGND
Supply
Supply
17, 18,
63, 64
G1, G2,
G7, G8,
H8
—
—
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
DV
25, 26,
61, 62
D8, E6,
F1, F2
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each side of the IC package are suggested,
such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
DD
separated from PLLV and AV internal to the device to provide noise
DD
DD
isolation. They should be tied at a low impedance point on the circuit
board.
ISO
CMOS
23
15
E8
H7
I
I
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1995
is implemented between the PDI1394P25 and LLC, the ISO terminal
should be tied low to enable the differentiation logic. If no isolation
barrier is implemented (direct connection), or bus holder isolation is
implemented, the ISO terminal should be tied high to disable the
differentiation logic.
LPS
CMOS 5 V tol
Link Power Status input. This terminal is used to monitor the
active/power status of the link layer controller and to control the state of
the PHY-LLC interface. This terminal should be connected to either the
V
supplying the LLC through a 10 kΩ resistor, or to a pulsed output
DD
which is active when the LLC is powered. A pulsed signal should be
used when an isolation barrier exists between the LLC and PHY. (See
Figure 8)
The LPS input is considered inactive if it is sampled low by the PHY for
more than 2.6 µs (128 SYSCLK cycles), and is considered active
otherwise (i.e., asserted steady high or an oscillating signal with a low
time less than 2.6 µs). The LPS input must be high for at least 21 ns in
order to be guaranteed to be observed as high by the PHY.
When the PDI1394P25 detects that LPS is inactive, it will place the
PHY-LLC interface into a low-power reset state. In the reset state, the
CTL and D outputs are held in the logic zero state and the LREQ input is
ignored; however, the SYSCLK output remains active. If the LPS input
remains low for more than 26 µs (1280 SYSCLK cycles), the PHY-LLC
interface is put into a low-power disabled state in which the SYSCLK
output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the
LCtrl register bit is set to 1, and is considered inactive if either the LPS
input is inactive or the LCtrl register bit is cleared to 0.
LREQ
NC
CMOS 5 V tol
No connect
1
H1
I
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P25. Bus holder is built into this terminal.
54, 55
—
These pins are not internally connected and consequently are “don’t
cares”. Other vendors’ pin compatible chips may require
connections and external circuitry on these pins.
NC
No connect
16, 43,
44, 45,
46, 47
A2, A3,
B3, B4,
C4
—
I
No connect.
PC0
PC1
PC2
CMOS 5 V tol
20
21
22
F7
E7
F8
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 21 for encoding.
PD
CMOS 5 V tol
14
G6
I
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. For more information, refer to Section 17.2
6
2001 Sep 06
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