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PCS3P625Z0XYG-08-TR PDF预览

PCS3P625Z0XYG-08-TR

更新时间： 2024-11-18 07:03:35
品牌 Logo 应用领域
PULSECORE /
页数 文件大小 规格书
15页 547K
描述
High Frequency Timing-Safe™ Peak EMI reduction IC

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PCS3P625Z0XYG-08-TR 技术参数

生命周期：Obsolete包装说明：4.40 MM, GREEN, TSSOP-8
Reach Compliance Code：unknown风险等级：5.84
JESD-30 代码：R-PDSO-G8逻辑集成电路类型：PLL BASED CLOCK DRIVER
端子数量：8封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified表面贴装：YES
端子形式：GULL WING端子位置：DUAL
Base Number Matches：1

PCS3P625Z0XYG-08-TR 数据手册

 浏览型号PCS3P625Z0XYG-08-TR的Datasheet PDF文件第2页浏览型号PCS3P625Z0XYG-08-TR的Datasheet PDF文件第3页浏览型号PCS3P625Z0XYG-08-TR的Datasheet PDF文件第4页浏览型号PCS3P625Z0XYG-08-TR的Datasheet PDF文件第5页浏览型号PCS3P625Z0XYG-08-TR的Datasheet PDF文件第6页浏览型号PCS3P625Z0XYG-08-TR的Datasheet PDF文件第7页 
PCS3P625Z05B/C  
PCS3P625Z09B/C  
May 2008  
rev 0.1  
High Frequency Timing-Safe™ Peak EMI reduction IC  
with Peak EMI reduction. PCS3P625Z05 is an eight-pin  
version, accepts one reference input and drives out five  
low-skew Timing-Safe™ clocks. PCS3P625Z09 accepts  
one reference input and drives out nine low-skew Timing-  
Safe™clocks.  
General Features  
•
High Frequency Clock distribution with Timing-  
Safe™ Peak EMI Reduction  
•
•
Input frequency range: 100MHz - 175MHz  
Multiple low skew Timing-safe™ Outputs:  
PCS3P625Z05: 5 Outputs  
PCS3P625Z05/09 has a DLY_CTRL for adjusting the  
Input-Output clock delay, depending upon the value of  
capacitor connected at this pin to GND.  
PCS3P625Z09: 9 Outputs  
•
•
•
•
External Input-Output Delay Control option  
Supply Voltage: 3.3V±0.3V  
PCS3P625Z05/09 operates from a 3.3V supply and is  
available in two different packages, as shown in the  
ordering information table, over commercial and Industrial  
temperature range.  
Commercial and Industrial temperature range  
Packaging Information:  
ASM3P625Z05: 8 pin SOIC, and TSSOP  
ASM3P625Z09:16 pin SOIC, and TSSOP  
True Drop-in Solution for Zero Delay Buffer,  
ASM5P2305A / 09A  
•
Application  
PCS3P625Z05/09 is targeted for use in Displays and  
memory interface systems.  
Functional Description  
PCS3P625Z05/09 is a versatile, 3.3V Zero-delay buffer  
designed to distribute high frequency Timing-Safe™ clocks  
General Block Diagram  
DLY_CTRL  
PLL  
DLY_CTRL  
PLL  
MUX  
CLKIN  
CLKOUTA1  
CLKOUTA2  
CLKOUTA3  
CLKOUT1  
CLKOUT2  
CLKOUT3  
CLKIN  
CLKOUTA4  
CLKOUTB1  
PCS3P625Z05B/C  
CLKOUT4  
S2  
S1  
Select Input  
Decoding  
CLKOUTB2  
CLKOUTB3  
CLKOUTB4  
PCS3P625Z05B/C  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  
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