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PCS3P7101AG-08ST PDF预览

PCS3P7101AG-08ST

更新时间: 2024-11-18 10:15:55
品牌 Logo 应用领域
PULSECORE 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
7页 311K
描述
Low Power Peak EMI Reducing clock synthesizer

PCS3P7101AG-08ST 技术参数

生命周期:Obsolete包装说明:GREEN, SOIC-8
Reach Compliance Code:unknown风险等级:5.84
Is Samacsys:NJESD-30 代码:R-PDSO-G8
长度:4.9 mm端子数量:8
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.45 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.91 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

PCS3P7101AG-08ST 数据手册

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September 2006  
rev 0.1  
PCS3P7101A  
Low Power Peak EMI Reducing clock synthesizer  
Product Description  
Features  
The PCS3P7101A is a low cost, single-output, clock  
synthesizer. The PCS3P7101A generates a 4x output clock  
from a 25 MHz standard fundamental mode, inexpensive  
crystal, or clock. It can replace multiple crystals and  
oscillators, saving valuable board space and cost. The  
device employs Spread Spectrum technique to reduce  
system electro-magnetic interference (EMI).  
Generates a 4x low EMI clock at the output  
Input frequency: 25 MHz  
Integrated loop filter components.  
Frequency deviation: ±0.25% (Typ) center spread  
Operates with a 3.3V Supply.  
The device also has a power-down feature that tri-state the  
clock output and turns off the PLL when the PD pin is taken  
low.  
Low power CMOS design.  
Available in 8-pin SOIC package.  
Pin compatible with ICS 341-22  
Block Diagram  
VDD  
PD  
PLL  
Modulation  
XIN/CLKIN  
XOUT  
Crystal  
Oscillator  
Frequency  
Divider  
Output  
Divider  
Phase  
Loop  
Filter  
VCO  
Detector  
Feedback  
Divider  
ModOUT  
VSS  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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