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PCS3I623Z05BG-08-SR PDF预览

PCS3I623Z05BG-08-SR

更新时间: 2024-11-19 08:19:47
品牌 Logo 应用领域
PULSECORE 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
15页 1380K
描述
Clock Generator, 50MHz, CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8

PCS3I623Z05BG-08-SR 技术参数

生命周期:Obsolete包装说明:0.150 INCH, GREEN, SOIC-8
Reach Compliance Code:unknown风险等级:5.84
JESD-30 代码:R-PDSO-G8长度:4.9 mm
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:50 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.91 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

PCS3I623Z05BG-08-SR 数据手册

 浏览型号PCS3I623Z05BG-08-SR的Datasheet PDF文件第2页浏览型号PCS3I623Z05BG-08-SR的Datasheet PDF文件第3页浏览型号PCS3I623Z05BG-08-SR的Datasheet PDF文件第4页浏览型号PCS3I623Z05BG-08-SR的Datasheet PDF文件第5页浏览型号PCS3I623Z05BG-08-SR的Datasheet PDF文件第6页浏览型号PCS3I623Z05BG-08-SR的Datasheet PDF文件第7页 
PCS3P623Z05A/B and PCS3P623Z09A/B  
Timing-Safe™ Peak EMI  
Reduction IC  
General Features  
Functional Description  
PCS3P623Z05/09 is a versatile, 3.3V Zero-delay buffer  
designed to distribute Timing-Safe™ clocks with Peak EMI  
reduction. PCS3P623Z05 is an eight-pin version, accepts  
one reference input and drives out five low-skew Timing-  
Safe™ clocks. PCS3P623Z09 accepts one reference input  
and drives out nine low-skew Timing-Safe™clocks.  
Clock distribution with Timing-Safe™ Peak EMI  
Reduction  
Input frequency range: 20MHz - 50MHz  
Multiple low skew Timing-safe™ Outputs:  
PCS3P623Z05: 5 Outputs  
PCS3P623Z09: 9 Outputs  
PCS3P623Z05/09 has a DLY_CTRL for adjusting the  
Input-Output clock delay, depending upon the value of  
capacitor connected at this pin to GND.  
External Input-Output Delay Control option  
Supply Voltage: 3.3V±0.3V  
Commercial and Industrial temperature range  
Packaging Information:  
PCS3P623Z05/09 operates from a 3.3V supply and is  
available in two different packages, as shown in the  
ordering information table, over commercial and Industrial  
temperature range.  
ASM3P623Z05: 8 pin SOIC, and TSSOP  
ASM3P623Z09:16 pin SOIC, and TSSOP  
True Drop-in Solution for Zero Delay Buffer,  
ASM5P2305A / 09A  
Application  
PCS3P623Z05/09 is targeted for use in Displays and  
memory interface systems.  
General Block Diagram  
DLY_CTRL  
PLL  
DLY_CTRL  
PLL  
MUX  
CLKIN  
CLKOUTA1  
CLKOUTA2  
CLKOUTA3  
CLKOUT1  
CLKOUT2  
CLKOUT3  
CLKIN  
CLKOUTA4  
CLKOUTB1  
PCS3P623Z05A/B  
CLKOUT4  
S2  
S1  
Select Input  
Decoding  
CLKOUTB2  
CLKOUTB3  
CLKOUTB4  
PCS3P623Z09A/B  
©2010 SCILLC. All rights reserved.  
January 2010 – Rev. 1  
Publication Order Number:  
PCS3P623Z05/D  

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