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PCS3I623Z05AG-16-TR PDF预览

PCS3I623Z05AG-16-TR

更新时间: 2024-02-13 14:23:21
品牌 Logo 应用领域
安森美 - ONSEMI PCS驱动光电二极管过程控制系统逻辑集成电路
页数 文件大小 规格书
13页 167K
描述
50MHz, OTHER CLOCK GENERATOR, PDSO16, 4.40 MM, GREEN, TSSOP-16

PCS3I623Z05AG-16-TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-16
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84系列:PCS3
JESD-30 代码:R-PDSO-G16长度:5 mm
负载电容(CL):30 pF逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.008 A功能数量:1
反相输出次数:端子数量:16
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
最大电源电流(ICC):27 mAProp。Delay @ Nom-Sup:0.35 ns
传播延迟(tpd):0.35 nsSame Edge Skew-Max(tskwd):0.7 ns
座面最大高度:1.1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
最小 fmax:50 MHzBase Number Matches:1

PCS3I623Z05AG-16-TR 数据手册

 浏览型号PCS3I623Z05AG-16-TR的Datasheet PDF文件第1页浏览型号PCS3I623Z05AG-16-TR的Datasheet PDF文件第3页浏览型号PCS3I623Z05AG-16-TR的Datasheet PDF文件第4页浏览型号PCS3I623Z05AG-16-TR的Datasheet PDF文件第5页浏览型号PCS3I623Z05AG-16-TR的Datasheet PDF文件第6页浏览型号PCS3I623Z05AG-16-TR的Datasheet PDF文件第7页 
PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B  
PLL  
DLY_CTRL  
CLKOUTA1  
CLKOUTA2  
CLKOUTA3  
CLKOUTA4  
CLKOUTB1  
CLKOUTB2  
CLKOUTB3  
CLKOUTB4  
MUX  
CLKIN  
PLL  
DLY_CTRL  
PCS3P623Z09A/B  
CLKIN  
CLKOUT1  
CLKOUT2  
CLKOUT3  
PCS3P623Z05A/B  
S2  
S1  
Select  
Input  
Decoding  
CLKOUT4  
Figure 1. General Block Diagrams  
Zero Delay and Skew Control  
Spread Spectrum Frequency Generation  
The clocks in digital systems are typically square waves  
with a 50% duty cycle and as frequencies increase the edge  
rates also get faster. Analysis shows that a square wave is  
composed of fundamental frequency and harmonics. The  
fundamental frequency and harmonics generate the energy  
peaks that become the source of EMI. Regulatory agencies  
test electronic equipment by measuring the amount of peak  
energy radiated from the equipment. In fact, the peak level  
allowed decreases as the frequency increases. The standard  
methods of reducing EMI are to use shielding, filtering,  
multilayer PCBs, etc. These methods are expensive.  
Spread spectrum clocking reduces the peak energy by  
reducing the Q factor of the clock. This is done by slowly  
modulating the clock frequency. The PCS3P623Z05/09 uses  
the center modulation spread spectrum technique in which  
the modulated output frequency varies above and below the  
reference frequency with a specified modulation rate. With  
center modulation, the average frequency is the same as the  
unmodulated frequency and there is no performance  
degradation.  
All outputs should be uniformly loaded to achieve Zero  
Delay between input and output. Since the DLY_CTRL pin  
is the internal feedback to the PLL, its relative loading can  
adjust the inputoutput delay.  
For applications requiring zero inputoutput delay, all  
outputs, including DLY_CTRL, must be equally loaded.  
Even if DLY_CTRL is not used, it must have a capacitive  
load equal to that on other outputs, for obtaining zero  
inputoutput delay.  
TimingSafe Technology  
TimingSafe technology is the ability to modulate a clock  
source with Spread Spectrum technology and maintain  
synchronization with any associated data path.  
http://onsemi.com  
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