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PCS3I2042BG-08-CR PDF预览

PCS3I2042BG-08-CR

更新时间: 2024-11-03 08:30:27
品牌 Logo 应用领域
PULSECORE 光电二极管
页数 文件大小 规格书
10页 348K
描述
PLL Based Clock Driver, 3I Series, 1 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, 2 X 2 MM, GREEN, TDFN-8

PCS3I2042BG-08-CR 数据手册

 浏览型号PCS3I2042BG-08-CR的Datasheet PDF文件第2页浏览型号PCS3I2042BG-08-CR的Datasheet PDF文件第3页浏览型号PCS3I2042BG-08-CR的Datasheet PDF文件第4页浏览型号PCS3I2042BG-08-CR的Datasheet PDF文件第5页浏览型号PCS3I2042BG-08-CR的Datasheet PDF文件第6页浏览型号PCS3I2042BG-08-CR的Datasheet PDF文件第7页 
PCS3P2042B  
LCD Panel EMI Reduction IC  
Features  
FCC approved method of EMI attenuation.  
Product Description  
The PCS3P2042B is  
frequency modulator designed specifically for digital flat  
panel applications. The PCS3P2042B reduces  
a versatile spread spectrum  
Provides up to 15dB of EMI suppression.  
Generates a low EMI spread spectrum clock of the  
input frequency.  
electromagnetic interference (EMI) at the clock source,  
allowing system wide reduction of EMI of down stream  
clock and data dependent signals. The PCS3P2042B  
allows significant system cost savings by reducing the  
number of circuit board layers ferrite beads, shielding and  
other passive components that are traditionally required to  
pass EMI regulations.  
Input frequency range: 30MHz - 100MHz.  
Output frequency range: 30MHz - 100MHz  
Optimized for 32.5MHz, 54MHz, 65MHz, 74MHz and  
108MHz pixel clock frequencies.  
Internal loop filter minimizes external components and  
board space.  
The PCS3P2042B uses the most efficient and optimized  
modulation profile approved by the FCC and is  
implemented in a proprietary all digital method.  
Eight selectable high spread ranges up to ±2%.  
Selectable spread options: Down Spread and Center  
Spread  
The PCS3P2042B modulates the output of a single PLL in  
order to “spread” the bandwidth of a synthesized clock,  
and more importantly, decreases the peak amplitudes of  
its harmonics. This results in significantly lower system  
EMI compared to the typical narrow band signal produced  
by oscillators and most frequency generators. Lowering  
EMI by increasing a signal‟s bandwidth is called „spread  
spectrum clock generation.‟  
SSON# control pin for spread spectrum enable and  
disable options.  
Low cycle-to-cycle jitter.  
3.3V ± 0.3V operating range.  
Low power CMOS design.  
Supports most mobile graphic accelerator and LCD  
timing controller specifications.  
Available in 8-pin SOIC, TSSOP and TDFN, COL  
(2X2) Packages.  
Applications  
Commercial and Industrial temperature range.  
The PCS3P2042B is targeted towards digital flat panel  
applications for notebook PCs, palm-size PCs, office  
automation equipments and LCD monitors.  
VDD  
Block Diagram  
SR0 CP1 CP0 SSON#  
PLL  
Modulation  
CLKIN  
Frequency  
Divider  
Output  
Divider  
Phase  
Detector  
Loop  
Filter  
VCO  
Feedback  
Divider  
ModOUT  
VSS  
©2010 SCILLC. All rights reserved.  
JANUARY 2010 Rev. 2  
Publication Order Number:  
PCS3P2042/D  

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