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PCD50922 PDF预览

PCD50922

更新时间: 2024-02-13 03:12:16
品牌 Logo 应用领域
恩智浦 - NXP 控制器
页数 文件大小 规格书
16页 93K
描述
Low cost; low power DECT baseband controllers ABC-PRO

PCD50922 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP80,.55SQ,20针数:80
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84JESD-30 代码:S-PQFP-G80
JESD-609代码:e3长度:12 mm
功能数量:1端子数量:80
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP80,.55SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH电源:3/3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Other Telecom ICs表面贴装:YES
技术:CMOS电信集成电路类型:CORDLESS TELEPHONE BASEBAND CIRCUIT
端子面层:TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:12 mm

PCD50922 数据手册

 浏览型号PCD50922的Datasheet PDF文件第1页浏览型号PCD50922的Datasheet PDF文件第2页浏览型号PCD50922的Datasheet PDF文件第4页浏览型号PCD50922的Datasheet PDF文件第5页浏览型号PCD50922的Datasheet PDF文件第6页浏览型号PCD50922的Datasheet PDF文件第7页 
Philips Semiconductors  
Objective specification  
Low cost; low power DECT baseband  
controllers (ABC-PRO)  
PCD509x2/zuu/v family  
1
FEATURES  
The PCD50912 is designed for GAP compatible DECT  
handsets  
The PCD50922 is designed for GAP compatible DECT  
base stations serving up to six handsets  
Fully static 80C51 microcontroller  
Comparator for use as bit-slicer  
Emulation supported for 80C51 program development  
Four 8-bit ports (P0, P1, P2 and P3), 32 I/O lines  
3 channel time-multiplexed 8-bit ADC for RSSI, battery  
and general input voltage measurement  
Dedicated port pins for keyboard, I2C-bus, interrupt  
sources and/or external memory  
Battery management supported by programmable  
current source for temperature or charge current  
measurement  
Fifteen interrupt sources (including those from TICB,  
BML and DSP) with two priority levels  
I2C-bus interface  
On-chip 8-bit DAC for various purposes  
Low power crystal oscillator at 13.824 MHz  
UART with IrDA-compatible Data Transmission Mode  
256 bytes of microcontroller main RAM  
3 kbytes of microcontroller AUX RAM  
1 kbyte of shared System Data RAM  
64 kbytes of mask programmable ROM  
Programmable on-chip capacitors for frequency  
adjustment to 13.824 MHz with large pulling range  
High performance DAC and ADC for dynamic earpiece  
and dynamic or electret microphone  
Analog-to-digital path switchable sensitivity for  
microphone or line interface input  
128 kbyte address space for external ROM access,  
maximum 192 kbytes together with internal ROM  
On-chip reference voltage and supply for electret  
microphone  
128 kbytes of external RAM addressable  
Embedded DSP with 6.912, 13.824 or 27.648 Mips  
Speech and IOM-2 interface  
Very low ohmic buzzer output  
Pulse density modulated or pulse width modulated  
buzzer output signal  
BML for TDMA frame (de)multiplexing. Transmission or  
reception can be programmed for any slot  
Power-on-reset  
Low power operation optimized for 2 battery cells in  
handset  
Ciphering, scrambling, CRC checking/generation,  
protected B-fields  
Long standby time due to reduced digital supply voltage  
and reduced activity in idle-locked mode  
Local call and B-field loop-back  
Automatic receiver delay adjustment programmable per  
slot to correct for terminal mobility  
Flexible supply voltage concept due to use of level  
shifters between each supply voltage domain  
Phase error measurement and phase error correction by  
hardware  
Eight independent supply voltage domains:  
– 1.8 to 3.6 V for digital core, microcontroller ports P0  
and P2, and also P1 and P3  
Serial interface to synthesizer for frequency  
programming  
– 1.8 to 3.6 V for buzzer, oscillator and battery  
– 2.7 to 3.6 V for RF interface and analog circuits  
CMOS technology  
Programmable timing and polarity of radio-control  
signals  
Easy interfacing with radio circuits, operating at different  
Small and flat LQFP80 package.  
supply voltages  
GMSK pulse shaper with two different pulse shapes  
(BT = 0.5 and BT = 0.8)  
1998 Apr 27  
3

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