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PCA9671DB PDF预览

PCA9671DB

更新时间: 2024-11-14 04:35:03
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
34页 196K
描述
Remote 16-bit I/O expander for Fm+ I2C-bus with reset

PCA9671DB 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP24,.24
针数:24Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.75JESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:8.2 mm
湿度敏感等级:1位数:16
I/O 线路数量:16端口数量:1
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.24
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:2.3/5.5 V认证状态:Not Qualified
座面最大高度:2 mm子类别:Parallel IO Port
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:5.3 mmuPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches:1

PCA9671DB 数据手册

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PCA9671  
Remote 16-bit I/O expander for Fm+ I2C-bus with reset  
Rev. 01 — 20 December 2006  
Product data sheet  
1. General description  
The PCA9671 provides general purpose remote I/O expansion for most microcontroller  
families via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus  
(Fm+) family.  
The PCA9671 is a drop in upgrade for the PCF8575 providing higher I2C-bus speeds  
(1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher  
I2C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without  
the need for bus buffers, higher total package sink capacity (400 mA versus 100 mA) that  
supports having all 25 mA LEDs on at the same time and more device addresses (64  
versus 8) to allow many more devices on the bus without address conflicts.  
The difference between the PCA9671 and the PCF8575 is that the interrupt output on the  
PCF8575 is replaced by a RESET input on the PCA9671.  
The device consists of a 16-bit quasi-bidirectional port and an I2C-bus interface. The  
PCA9671 has a low current consumption and includes latched outputs with 25 mA high  
current drive capability for directly driving LEDs. The internal Power-On Reset (POR),  
hardware reset pin (RESET) or software reset sequence initializes the I/Os as inputs.  
2. Features  
I 1 MHz I2C-bus interface  
I Compliant with the I2C-bus Fast-mode and Standard-mode  
I SDA with 30 mA sink capability for 4000 pF buses  
I 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os  
I 16-bit remote I/O pins that default to inputs at power-up  
I Latched outputs with 25 mA sink capability for directly driving LEDs  
I Total package sink capability of 400 mA  
I Active LOW reset input  
I 64 programmable slave addresses using 3 address pins  
I Readable device ID (manufacturer, device type, and revision)  
I Low standby current  
I 40 °C to +85 °C operation  
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per  
JESD22-A115, and 1000 V CDM per JESD22-C101  
I Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA  
I Packages offered: SO24, SSOP24, QSOP24, TSSOP24, HVQFN24, DHVQFN24  

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